中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.012 seconds)

    WIRELESS COMMUNICATION WITHIN A CONTROL PLANE AND A DATA PLANE
    3.
    发明申请
    WIRELESS COMMUNICATION WITHIN A CONTROL PLANE AND A DATA PLANE 有权

    公开(公告)号：US20220200776A1

    公开(公告)日：2022-06-23

    申请号：US17131862

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Brent R. CARLTON ,  Richard DORRANCE ,  Kenneth P. FOUST ,  Asma Beevi KURIPARAMBIL THEKKUMPATE ,  Renzhi LIU ,  Rinkle JAIN

    IPC: H04L5/14 ,  H04W52/02 ,  H04W74/00 ,  H04L25/03 ,  H04B1/44

    Abstract: A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.

    IN-MEMORY ANALOG CHANNEL EQUALIZATION
    4.
    发明公开
    IN-MEMORY ANALOG CHANNEL EQUALIZATION 审中-公开

    公开(公告)号：US20240113698A1

    公开(公告)日：2024-04-04

    申请号：US17956844

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Richard DORRANCE ,  Peter SAGAZIO ,  Renzhi LIU ,  Hechen WANG ,  Deepak DASALUKUNTE ,  Brent R. CARLTON

    IPC: H03H17/02

    CPC classification number: H03H17/02 ,  H03H2218/10

    Abstract: A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.

Patent Agency Ranking