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    LOW LOSS TRANSMITTER RECEIVER SWITCH WITH TRANSFORMER MATCHING NETWORK
    2.
    发明申请
    LOW LOSS TRANSMITTER RECEIVER SWITCH WITH TRANSFORMER MATCHING NETWORK 有权

    公开(公告)号：US20210044318A1

    公开(公告)日：2021-02-11

    申请号：US16931462

    申请日：2020-07-17

    Applicant: Intel Corporation

    Inventor： Steven CALLENDER ,  Christopher HULL ,  Stefano PELLERANO ,  Woorim SHIN ,  Ka Chun KWOK

    IPC: H04B1/48 ,  H03F1/56 ,  H03F3/21 ,  H03H7/38

    Abstract: A transmit receive switch (TRSW) system is disclosed. The system has a transmission line, a transformer based matching network, a shunt switch, an amplifier and circuitry. The transmission line is connected to an antenna port. The transformer based matching network is connected to the transmission line and has a first coil and a second coil, wherein the second coil is connected to the transmission line. The amplifier can be configured as a shunt switch when inactive. The shunt switch, including the amplifier configured as the shunt switch, can be connected to the first coil of the transformer based matching network. The circuitry is configured to cause the shunt switch to be ON during an inactive mode and create a short across the first coil. Combined, the length of transmission line needed to complete the impedance transformation is reduced, thereby lowering the overall insertion loss of the transmit/receive switch.

    PHASE MULTIPLEXER
    3.
    发明申请
    PHASE MULTIPLEXER 有权
    相位多路复用器

    公开(公告)号：US20150303939A1

    公开(公告)日：2015-10-22

    申请号：US14155327

    申请日：2014-01-14

    Applicant: Intel Corporation

    Inventor： Paolo MADOGLIO ,  Stefano PELLERANO

    IPC: H03M1/82 ,  H03M1/08 ,  G06F1/08 ,  H03M1/66

    CPC classification number: H03M1/822 ,  G06F1/04 ,  G06F1/08 ,  H03K5/131 ,  H03K2005/00045 ,  H03L7/16 ,  H03M1/0836 ,  H03M1/662

    Abstract: Representative implementations of devices and techniques provide a phase multiplexer that may be associated with at least a communication device. The described phase multiplexer may be able to switch between input phases without distorting a pulse width of a given input phase. In one implementation, this is achieved by enabling one phase at a time. More specifically, a gating window specific for each given phase is provided. The gating window is designed to avoid glitches associated with signals at an output of the phase multiplexer. Furthermore, the gating window is designed to avoid the generation of pulse width modifications.

    Abstract translation: 设备和技术的代表性实现提供了可以与至少一个通信设备相关联的相位多路复用器。 所描述的相位多路复用器可能能够在输入相位之间切换，而不会使给定输入相位的脉冲宽度变形。 在一个实现中，这是通过一次启用一个阶段来实现的。 更具体地，提供对于每个给定相位特定的门控窗口。 门控窗口旨在避免与相位多路复用器输出端的信号相关的毛刺。 此外，门控窗口被设计为避免产生脉冲宽度修改。

    ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
    4.
    发明公开
    ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20240097693A1

    公开(公告)日：2024-03-21

    申请号：US17933512

    申请日：2022-09-20

    Applicant: Intel Corporation

    Inventor： Somnath KUNDU ,  Amy L. WHITCOMBE ,  Stefano PELLERANO ,  Peter SAGAZIO ,  Brent CARLTON

    IPC: H03M1/10 ,  H04B1/40

    CPC classification number: H03M1/1014 ,  H04B1/40

    Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

    RADIO COMMUNICATION CIRCUIT WITH RADIO FREQUENCY QUADRATURE GENERATION
    9.
    发明申请
    RADIO COMMUNICATION CIRCUIT WITH RADIO FREQUENCY QUADRATURE GENERATION 有权

    公开(公告)号：US20220407544A1

    公开(公告)日：2022-12-22

    申请号：US17353840

    申请日：2021-06-22

    Applicant: Intel Corporation

    Inventor： Woorim SHIN ,  Ritesh A. BHAT ,  Chuanzhao YU ,  Stefano PELLERANO

    IPC: H04B1/04 ,  H04B1/30 ,  H01Q21/24

    Abstract: Radio communication circuits, radio transmitters, and methods are provided in this disclosure. The radio communication circuit may include a modulator configured to provide a first modulated signal including a carrier signal at a carrier frequency, and a second modulated signal including the carrier signal at the carrier frequency. The radio communication circuit may further include a phase shift generator configured to receive a first signal based on the first modulated signal and a second signal based on the second modulated signal. The phase shift generator of the radio communication circuit may further be configured to provide a predefined phase difference between the first signal and the second signal.

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