公开(公告)号：US10185349B2

公开(公告)日：2019-01-22

申请号：US14917928

申请日：2013-12-03

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert Fulton

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/183 ,  G06F13/36 ,  G06F13/40

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

公开(公告)号：US11144088B2

公开(公告)日：2021-10-12

申请号：US16430170

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Jagannadha Rao V. V. V. Rapeta ,  Mikal Hunsaker ,  Ronald Swartz ,  Robert Fulton ,  L. Mark Elzinga ,  Young Min Park ,  David R. Mulvihill

IPC: G06F1/12 ,  G06F13/42

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

公开(公告)号：US20190332139A1

公开(公告)日：2019-10-31

申请号：US16430170

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Jagannadha Rao V. V. V. Rapeta ,  Mikal Hunsaker ,  Ronald Swartz ,  Robert Fulton ,  L. Mark Elzinga ,  Young Min Park ,  David R. Mulvihill

IPC: G06F1/12 ,  G06F13/42

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.