公开(公告)号：US10712768B2

公开(公告)日：2020-07-14

申请号：US16252471

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert R. Fulton

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/183 ,  G06F13/36 ,  G06F13/40

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

公开(公告)号：US20190220054A1

公开(公告)日：2019-07-18

申请号：US16252471

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert R. Fulton

IPC: G06F1/08 ,  G06F13/40 ,  H03L7/183 ,  G06F13/36

CPC classification number: G06F1/08 ,  G06F13/36 ,  G06F13/4068 ,  H03L7/183 ,  H03L2207/50

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

公开(公告)号：US10185349B2

公开(公告)日：2019-01-22

申请号：US14917928

申请日：2013-12-03

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert Fulton

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/183 ,  G06F13/36 ,  G06F13/40

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.