公开(公告)号：US20210096778A1

公开(公告)日：2021-04-01

申请号：US17122158

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh NAGARAJAN ,  Anoop MUKKER ,  Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F3/06

Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

公开(公告)号：US20190042140A1

公开(公告)日：2019-02-07

申请号：US15953367

申请日：2018-04-13

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Romesh TRIVEDI ,  Suresh NAGARAJAN ,  Sriram NATARAJAN

IPC: G06F3/06

Abstract: An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.

公开(公告)号：US20210097004A1

公开(公告)日：2021-04-01

申请号：US17122152

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh NAGARAJAN ,  Scott CRIPPIN ,  Sahar KHALILI ,  Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F12/1009

Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

公开(公告)号：US20210109587A1

公开(公告)日：2021-04-15

申请号：US17129116

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Anoop MUKKER ,  Romesh TRIVEDI ,  Suresh NAGARAJAN

IPC: G06F1/3234 ,  G06F1/3221 ,  G06F1/20

Abstract: Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

公开(公告)号：US20190042444A1

公开(公告)日：2019-02-07

申请号：US15957650

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F12/0871 ,  G06F12/02

Abstract: A solid state drive (SSD) includes different segments of nonvolatile (NV) storage media with different access times. The NV media segment with faster access time operates as a cache for the segment with the slower access time. The SSD implements idle eviction from the cache segment to the other segment based on an idle condition of the SSD. The SSD can dynamically change application of the idle eviction based on a power management state indicated for the hardware platform. Thus, a change in power management state of the hardware platform associated with the SSD can cause the SSD to implement idle eviction differently.