公开(公告)号：US20210109587A1

公开(公告)日：2021-04-15

申请号：US17129116

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Anoop MUKKER ,  Romesh TRIVEDI ,  Suresh NAGARAJAN

IPC: G06F1/3234 ,  G06F1/3221 ,  G06F1/20

Abstract: Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

公开(公告)号：US20210096778A1

公开(公告)日：2021-04-01

申请号：US17122158

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh NAGARAJAN ,  Anoop MUKKER ,  Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F3/06

Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.