公开(公告)号：US20190332869A1

公开(公告)日：2019-10-31

申请号：US16379176

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： MAYURESH M. VARERKAR ,  BARNAN DAS ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  SACHIN GODSE ,  FARSHAD AKHBARI ,  NARAYAN SRINIVASA ,  ALTUG KOKER ,  NADATHUR RAJAGOPALAN SATISH ,  DUKHWAN KIM ,  FENG CHEN ,  ABHISHEK R. APPU ,  JOYDEEP RAY ,  PING T. TANG ,  MICHAEL S. STRICKLAND ,  XIAOMING CHEN ,  ANBANG YAO ,  TATIANA SHPEISMAN ,  VASANTH RANGANATHAN ,  SANJEEV JAHAGIRDAR

IPC: G06K9/00 ,  G06N3/063 ,  G06T1/20 ,  G06N3/08 ,  G06N3/04

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

公开(公告)号：US20210041934A1

公开(公告)日：2021-02-11

申请号：US17080395

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： KINCHIT DESAI ,  SANJEEV JAHAGIRDAR ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY

IPC: G06F1/3237 ,  G06N3/04 ,  G06N3/08 ,  G06F1/3234 ,  G06F1/3206

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

公开(公告)号：US20190041961A1

公开(公告)日：2019-02-07

申请号：US16144538

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： KINCHIT DESAI ,  SANJEEV JAHAGIRDAR ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY

IPC: G06F1/32 ,  G06N3/08 ,  G06N3/04

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.