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公开(公告)号:US11237620B2
公开(公告)日:2022-02-01
申请号:US16866416
申请日:2020-05-04
Applicant: Intel Corporation
Inventor: Dileep J. Kurian , Pranjali S. Deshmukh , Sriram Kabisthalam Muthukumar , Ankit Gupta , Tanay Karnik , David Arditti Ilitzky , Saurabh Bhandari
IPC: G06F1/32 , G06F1/3287 , G06F1/3296 , G06F1/324
Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.
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公开(公告)号:US20200264691A1
公开(公告)日:2020-08-20
申请号:US16866416
申请日:2020-05-04
Applicant: Intel Corporation
Inventor: Dileep J. Kurian , Pranjali S. Deshmukh , Sriram Kabisthalam Muthukumar , Ankit Gupta , Tanay Karnik , David Arditti Ilitzky , Saurabh Bhandari
IPC: G06F1/3287 , G06F1/324 , G06F1/3296
Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.
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公开(公告)号:US20190094949A1
公开(公告)日:2019-03-28
申请号:US15719483
申请日:2017-09-28
Applicant: Intel Corporation
Inventor: Dileep J. Kurian , Pranjali S. Deshmukh , Sriram Kabisthalam Muthukumar , Ankit Gupta , Tanay Karnik , David Arditti Ilitzky , Saurabh Bhandari
Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.
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