公开(公告)号：US11422939B2

公开(公告)日：2022-08-23

申请号：US16727657

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Ravi K. Venkatesan ,  Shlomi Shua ,  Oz Shitrit ,  Michael Behar ,  Roni Rosner

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/126

Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.

公开(公告)号：US11151074B2

公开(公告)日：2021-10-19

申请号：US16542085

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Roni Rosner ,  Ravi Venkatesan ,  Shlomi Shua ,  Oz Shitrit ,  Henrietta Bezbroz ,  Alexander Gendler ,  Ohad Falik ,  Zigi Walter ,  Michael Behar ,  Shlomi Alkalay

IPC: G06F13/42 ,  G06N3/04 ,  G06F13/20 ,  G06F12/0893

Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.