公开(公告)号：US11422939B2

公开(公告)日：2022-08-23

申请号：US16727657

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Ravi K. Venkatesan ,  Shlomi Shua ,  Oz Shitrit ,  Michael Behar ,  Roni Rosner

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/126

Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.

公开(公告)号：US20180173637A1

公开(公告)日：2018-06-21

申请号：US15387429

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Eran Shifer ,  Ravi K. Venkatesan ,  Leon Polishuk ,  Anant V. Nori ,  Ori Lempel ,  Manikantan R

IPC: G06F12/0891 ,  G06F12/0815

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/1024 ,  G06F2212/62

Abstract: An indication of a first cache entry to be removed from a cache, the first cache entry corresponding to a first memory address in a memory may be received. A second memory address in the memory based at least in part on the first memory address may be identified. A request to identify a second cache entry in the cache corresponding to the second memory address and to determine whether a removal policy is satisfied may be sent. A response to the request, the response comprising an indication of the second cache entry to be removed from the cache based at least in part on the request may be sent. The first cache entry and the second cache entry from the cache may be removed. Data corresponding to the first and second cache entries to the memory with a single page file access may be written.