公开(公告)号：US20220058765A1

公开(公告)日：2022-02-24

申请号：US17466591

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Eric G. LISKAY ,  Prasoonkumar SURTI ,  Sudhakar KAMMA ,  Karthik VAIDYANATHAN ,  Rajasekhar PANTANGI ,  Altug KOKER ,  Abhishek RHISHEEKESAN ,  Shashank LAKSHMINARAYANA ,  Priyanka LADDA ,  Karol A. SZERSZEN

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/38

Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.

公开(公告)号：US20250094277A1

公开(公告)日：2025-03-20

申请号：US18966942

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Kishore KASICHAINULA ,  Thierry BEAUMONT ,  Dhanumjai PASUMARTHY ,  Sudhakar KAMMA

IPC: G06F11/10

Abstract: Methods and apparatus for low latency fail-operational Time Sensitive Networking. An apparatus includes an error detection and path switching (EDPS) circuit comprising circuitry to read data from volatile memory, detect whether read data is errant, the errant data including one or more uncorrectable errors, and send a message to access correct data corresponding to the errant data stored in a non-volatile memory device, the message identifying the correct data to be returned to the EDPS circuit. The apparatus receives the correct data and enables the correct data to be read by circuitry coupled to the EPDS circuit. The EDPS circuit includes Error Correction Code (ECC) logic to detect uncorrectable errors, detect the data has no ECC errors, and detect and correct single-bit errors to obtain corrected data. Data with no ECC errors and corrected data is immediately made available for reading by the circuitry coupled to the EPDS circuit.

公开(公告)号：US20210142438A1

公开(公告)日：2021-05-13

申请号：US16683024

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Eric G. LISKAY ,  Prasoonkumar SURTI ,  Sudhakar KAMMA ,  Karthik VAIDYANATHAN ,  Rajasekhar PANTANGI ,  Altug KOKER ,  Abhishek RHISHEEKESAN ,  Shashank LAKSHMINARAYANA ,  Priyanka LADDA ,  Karol A. Szerszen

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/50

Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.