公开(公告)号：US20230096188A1

公开(公告)日：2023-03-30

申请号：US17485262

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Abhishek R. APPU ,  John H. FEIT

IPC: G06T15/00 ,  G06T1/60 ,  G06T3/00

Abstract: Examples include techniques for a fast clear of a 3-dimensional (3D) surface. Examples include re-describing 3D surface to a 2D surface using various dimension of the 3D surface as inputs in an algorithm to output a 2-dimensional (2D) surface as a re-description of the 3D surface. The algorithm to also includes additional inputs associated with a tiling mode used to read or write the 3D surface to a graphics display and a bit per pixel format to output the 2D surface. 2D surface width and height associated with the outputted 2D surface is included in a clear command to cause the 3D surface to be cleared.

公开(公告)号：US20230205704A1

公开(公告)日：2023-06-29

申请号：US17561652

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Prasoonkumar SURTI ,  Vidhya KRISHNAN ,  Abhishek R. APPU ,  Karol A. SZERSZEN ,  Lakshminarayanan STRIRAMASSARMA

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/401

Abstract: A graphics processor includes multiple levels of memory units, including a memory device and a cache device located near a graphics component. The graphics processor includes distributed compression/decompression, including a module between the cache device and the memory device. The module can perform compression of write data when the write data is moved from the cache device to the memory device, and perform decompression of read data when the read data is moved from the memory device to the cache device. The graphics processor can include a second level of cache with another compression module between the first level of cache and the second level of cache.

公开(公告)号：US20230062540A1

公开(公告)日：2023-03-02

申请号：US17405957

申请日：2021-08-18

Applicant: Intel Corporation

Inventor： Prasoonkumar SURTI ,  Abhishek R. APPU ,  Karol A. SZERSZEN ,  Karthik VAIDYANATHAN ,  Sreenivas KOTHANDARAMAN ,  Mohamed FAROOK

IPC: G06T9/00 ,  H03M7/30

Abstract: Examples described herein relate to a manner of determining a number of bits to encode compression data. Some examples include: compressing pixel data of a region of pixels in a frame; determining a number of bits associated with at least two partitions; utilizing the determined number of bits to encode residual values generated from the compressing the pixel data; and storing the encoded residual values. In some examples, the at least two partitions comprise a first partition and a second partition. Some examples include: encoding residuals in the first partition using a number of bits associated with the first partition and encoding residuals in the second partition using a number of bits associated with the second partition. Some examples include: determining a distribution of bins of residuals, wherein each different bin represents a number of bits used to encode a residual value and determining a midpoint of a total number of residuals as a bin that stores a residual that is approximately 50 percentile of the total number of residuals of the distribution.

公开(公告)号：US20230030741A1

公开(公告)日：2023-02-02

申请号：US17390661

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Nilay MISTRY ,  Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Ronald W. SILVAS

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/30

Abstract: Compressed verbatim copy can enable more efficient copying of compressed data. In one example, a compressed verbatim copy method involves receiving a command to copy compressed data from a source address of the memory device to a destination address. In response to the receipt of the command, the method involves copying the compressed data in a compressed format from the source address to the destination address without first decompressing the data. A second source address and a second destination address of metadata for the compressed data is determined, and the metadata is copied from the second source address to the second destination address.

公开(公告)号：US20230206383A1

公开(公告)日：2023-06-29

申请号：US17561666

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Vidhya KRISHNAN ,  Aditya NAVALE ,  Abhishek R. APPU ,  Altug KOKER ,  Ronald W. SILVAS

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/084

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/084 ,  G06F2212/401

Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

公开(公告)号：US20230099093A1

公开(公告)日：2023-03-30

申请号：US17484782

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Abhishek R. APPU

IPC: G06F9/54 ,  G06T1/20 ,  G06T1/60 ,  H04L29/06

Abstract: A graphics processing apparatus includes graphics processors connected by a network connection, where the graphics processors pass compressed data. A first graphics processor stores data blocks as compressed data in a memory. The compressed data has data blocks of variable size, where a size of a block of compressed data depends on a compression ratio of the block of compressed data. A second graphics processor also stores data blocks as compressed data. The first graphics processor concatenates a variable number of blocks of compressed data into a packet of fixed size to send to the second graphics processor. The packet has a variable number of blocks of compressed data depending on the compression ratios of the multiple blocks of compressed data.

公开(公告)号：US20220058765A1

公开(公告)日：2022-02-24

申请号：US17466591

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Eric G. LISKAY ,  Prasoonkumar SURTI ,  Sudhakar KAMMA ,  Karthik VAIDYANATHAN ,  Rajasekhar PANTANGI ,  Altug KOKER ,  Abhishek RHISHEEKESAN ,  Shashank LAKSHMINARAYANA ,  Priyanka LADDA ,  Karol A. SZERSZEN

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/38

Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.