公开(公告)号：US20240004713A1

公开(公告)日：2024-01-04

申请号：US18363339

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU ,  Joydeep RAY ,  Kamal SINHA ,  Prasoonkumar SURTI ,  Kiran C. VEERNAPU ,  Subramaniam MAIYURAN ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F1/329 ,  G06F9/4893 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  Y02D10/00 ,  G06T2200/28

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230038862A1

公开(公告)日：2023-02-09

申请号：US17855721

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Balaji CHANDRASEKHARAN ,  Jayakrishna S ,  Pattabhiraman K ,  Altug KOKER

IPC: G06F9/50

Abstract: Examples include techniques to arbitrate a plurality of input requests received from input clients that request data to be stored or placed in a destination. An arbiter may be arranged to grant an input request based on an assigned weight and based on an indication that the destination is ready to receive the data to be stored or placed in the destination.

公开(公告)号：US20210287327A1

公开(公告)日：2021-09-16

申请号：US17182256

申请日：2021-02-23

Applicant: INTEL CORPORATION

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Altug KOKER ,  Balaji VEMBU ,  Pattabhiraman K ,  Matthew B. CALLAWAY

IPC: G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US20200320177A1

公开(公告)日：2020-10-08

申请号：US16792822

申请日：2020-02-17

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Abhishek R. APPU ,  Pattabhiraman K ,  Balaji VEMBU ,  Altug KOKER

IPC: G06F21/10 ,  G06F12/14 ,  G06F12/0895 ,  G06F9/455 ,  G06F12/0815 ,  G06T15/00 ,  H04N19/00 ,  H04N21/4405

Abstract: An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.

公开(公告)号：US20200211970A1

公开(公告)日：2020-07-02

申请号：US16236228

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Rajabali KODURI ,  Leonard NEIBERG ,  Altug KOKER ,  Swaminathan SIVAKUMAR

IPC: H01L23/538 ,  H01L23/528 ,  H01L25/18 ,  H01L23/00 ,  H01L21/66 ,  H01L21/78

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

公开(公告)号：US20220398147A1

公开(公告)日：2022-12-15

申请号：US17849356

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Balaji VEMBU ,  Bryan WHITE ,  Ankur SHAH ,  Murali RAMADOSS ,  David PUFFER ,  Altug KOKER ,  Aditya NAVALE ,  Mahesh NATU

IPC: G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20210391301A1

公开(公告)日：2021-12-16

申请号：US16898198

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Debendra MALLIK ,  Altug KOKER

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die electronic packages. In an embodiment, an electronic package comprises a package substrate and a first die electrically coupled to the package substrate. In an embodiment, an array of die stacks are electrically coupled to the first die. In an embodiment the array of die stacks are between the first die and the package substrate. In an embodiment, individual ones of the die stacks comprise a plurality of second dies arranged in a vertical stack.

公开(公告)号：US20210149680A1

公开(公告)日：2021-05-20

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. APPU

IPC: G06F9/38 ,  G06F12/084 ,  G06F9/54 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20200278938A1

公开(公告)日：2020-09-03

申请号：US16700853

申请日：2019-12-02

Applicant: INTEL CORPORATION

Inventor： Balaji VEMBU ,  Altug KOKER ,  Joydeep RAY ,  Abhishek R. APPU ,  Pattabhiraman K ,  Niranjan L. COORAY

IPC: G06F13/16 ,  G06F13/40 ,  G06T1/60 ,  G06F9/50

Abstract: An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

公开(公告)号：US20200005427A1

公开(公告)日：2020-01-02

申请号：US16505555

申请日：2019-07-08

Applicant: INTEL CORPORATION

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Altug KOKER ,  Balaji VEMBU ,  Pattabhiraman K. ,  Matthew B. CALLAWAY

IPC: G06T1/60 ,  G06F9/455 ,  G06F9/48 ,  G06T15/00 ,  G06F9/50

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.