公开(公告)号：US09870339B2

公开(公告)日：2018-01-16

申请号：US14752047

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T. J. O'Dwyer ,  Serge Zhilyaev

IPC: G06F15/76 ,  G06F13/36 ,  G06F15/80 ,  G06F13/16 ,  G06F13/40 ,  G06F9/38

CPC classification number: G06F15/8061 ,  G06F9/30036 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3877 ,  G06F13/16 ,  G06F13/4059

Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

公开(公告)号：US10216483B2

公开(公告)日：2019-02-26

申请号：US15696036

申请日：2017-09-05

Applicant: Intel Corporation

Inventor： T. J. O'Dwyer ,  Pierre Laurent

IPC: G06F7/523

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.

公开(公告)号：US09778910B2

公开(公告)日：2017-10-03

申请号：US14664669

申请日：2015-03-20

Applicant: Intel Corporation

Inventor： T. J. O'Dwyer ,  Pierre Laurent

IPC: G06F7/10 ,  G06F7/38 ,  G06F7/533 ,  G06F7/72

CPC classification number: G06F7/533 ,  G06F7/723

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.

公开(公告)号：US09753692B2

公开(公告)日：2017-09-05

申请号：US14668349

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： T. J. O'Dwyer ,  Pierre Laurent

IPC: G06F7/38 ,  G06F7/523

CPC classification number: G06F7/523

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.