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    HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING
    2.
    发明申请
    HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING 有权
    硬件处理器和轻巧耦合异构计算的方法

    公开(公告)号：US20160378715A1

    公开(公告)日：2016-12-29

    申请号：US14752047

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T.J. O'Dwyer ,  Serge Zhilyaev

    IPC: G06F15/80

    CPC classification number: G06F15/8061 ,  G06F9/30036 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3877 ,  G06F13/16 ,  G06F13/4059

    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

    Abstract translation: 描述了与紧耦合异构计算有关的方法和设备。 在一个实施例中，硬件处理器并行地包括多个执行单元，用于将多个执行单元的输入连接到第一缓冲器和多个存储器组的输出并连接多个存储体的输入的开关和 与第一缓冲器，多个存储体和多个执行单元的输出并联的多个第二缓冲器，以及具有连接到多个第二缓冲器的输出的输入的卸载引擎。

    Parallelized authentication encoding
    5.
    发明授权
    Parallelized authentication encoding 有权

    公开(公告)号：US10140458B2

    公开(公告)日：2018-11-27

    申请号：US15093200

    申请日：2016-04-07

    Applicant: Intel Corporation

    Inventor： Chang Yong Kang ,  Pierre Laurent

    IPC: G06F12/14 ,  G06F21/60 ,  G06F9/30 ,  G06F9/38 ,  G06F21/64

    Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.

    PARALLELIZED AUTHENTICATION ENCODING
    7.
    发明申请
    PARALLELIZED AUTHENTICATION ENCODING 审中-公开

    公开(公告)号：US20170293765A1

    公开(公告)日：2017-10-12

    申请号：US15093200

    申请日：2016-04-07

    Applicant: Intel Corporation

    Inventor： Chang Yong Kang ,  Pierre Laurent

    IPC: G06F21/60 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30101 ,  G06F9/3867 ,  G06F21/64

    Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.

    PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE
    8.
    发明申请
    PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中提供多个引脚

    公开(公告)号：US20160357700A1

    公开(公告)日：2016-12-08

    申请号：US14880443

    申请日：2015-10-12

    Applicant: Intel Corporation

    Inventor： Michael T. Klinglesmith ,  Chang Yong Kang ,  Robert DeGruijl ,  Ioannis T. Schoinas ,  Darren Abramson ,  Khee Wooi Lee

    IPC: G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  G06F3/06

    CPC classification number: G06F13/4282 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/068 ,  G06F12/0828 ,  G06F13/1663 ,  G06F2212/621

    Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，系统包括：与第一根空间标识符相关联并包括至少一个第一主处理器和第一代理的第一根空间，所述至少一个第一主处理器和与第一根空间标识符相关联的第一代理 ; 与第二根空间标识符相关联并且包括至少一个第二主处理器和第二代理的第二根空间，所述至少一个第二主处理器和与所述第二根空间标识符相关联的第二代理; 以及共享结构，用于耦合第一根空间和第二根空间，共享结构至少部分地基于事务的根空间字段将事务路由到第一根空间或第二根空间。 描述和要求保护其他实施例。

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