公开(公告)号：US20230333928A1

公开(公告)日：2023-10-19

申请号：US18212057

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Todd HINCK ,  Kuljit S. BAINS

IPC: G06F11/10 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/1435 ,  G06F11/0784

Abstract: Techniques for storing and accessing metadata within selective dynamic random access memory (DRAM) devices are described. In one example, a dual in-line memory module (DIMM) includes a plurality of dynamic random access memory (DRAM) devices, wherein each of plurality of DRAM devices includes on-die ECC bits. At least one of the plurality of DRAM devices includes circuitry to provide access to read from and write to the on-die ECC bits of the DRAM device. The DIMM includes one or more pins to transmit metadata to and from the on-die ECC bits of the DRAM device.

公开(公告)号：US20230215493A1

公开(公告)日：2023-07-06

申请号：US18120907

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Duane E. GALBI ,  Matthew J. ADILETTA ,  Mohammad M. RASHID ,  Todd HINCK ,  Vijaya K. BODDU

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/4096

Abstract: Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.