公开(公告)号：US20230215493A1

公开(公告)日：2023-07-06

申请号：US18120907

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Duane E. GALBI ,  Matthew J. ADILETTA ,  Mohammad M. RASHID ,  Todd HINCK ,  Vijaya K. BODDU

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/4096

Abstract: Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.

公开(公告)号：US20240193109A1

公开(公告)日：2024-06-13

申请号：US18444379

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Michelle M. WIGTON ,  Kambiz R. MUNSHI ,  Zhongyao Linda GU ,  Mohammad M. RASHID ,  Victor LAU ,  Jing LING

IPC: G06F13/16 ,  H10B12/00

CPC classification number: G06F13/1689 ,  H10B12/00

Abstract: Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.

公开(公告)号：US20220358061A1

公开(公告)日：2022-11-10

申请号：US17873035

申请日：2022-07-25

Applicant: Intel Corporation

Inventor： Jai Ram SILIVERI ,  Pooja K. JADHAV ,  Sampath DAKSHINAMURTHY ,  Mohammad M. RASHID ,  Lohit YERVA

IPC: G06F13/16

Abstract: In a memory subsystem, a physical interface (PHY) has an unmatched architecture. To compensate for the unmatched architecture, the PHY has variable delay compensation to adjust for propagation mismatch of analog signals in the data (DQ) path and data strobe (DQS) path of the PHY. The variable delay compensation can be provided by adjusting the operation of a digital component of the PHY to introduce the delay compensation.