公开(公告)号：US20160358652A1

公开(公告)日：2016-12-08

申请号：US14731212

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sandeep K. Guliani ,  Ved Pragyan

IPC: G11C13/00 ,  G06F12/08

CPC classification number: G11C13/0097 ,  G06F12/0891 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/76

Abstract: Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于向诸如相变存储器（PCM）设备的非易失性随机存取存储器（NVRAM）提供复位电流的技术和配置。 在一个实施例中，该装置可以包括NVRAM装置; 与NVRAM器件耦合以将选择镜电压施加到NVRAM器件的选择镜电路，以选择NVRAM器件的存储器单元; 以及与NVRAM器件耦合的复位镜电路，以在施加选择镜电压之后将复位镜电压施加到NVRAM器件的存储单元，以复位存储器单元。 复位镜电压可以低于选择镜电压，以便于将高于电流阈值的复位电流传送到存储器单元。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09715930B2

公开(公告)日：2017-07-25

申请号：US14731212

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sandeep K. Guliani ,  Ved Pragyan

IPC: G11C13/00 ,  G06F12/0891

CPC classification number: G11C13/0097 ,  G06F12/0891 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/76

Abstract: Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.