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    MULTISTAGE MEMORY CELL READ
    1.
    发明申请
    MULTISTAGE MEMORY CELL READ 有权

    公开(公告)号：US20160217853A1

    公开(公告)日：2016-07-28

    申请号：US14846898

    申请日：2015-09-07

    Applicant: Intel Corporation

    Inventor： Sandeep K. Guliani ,  Kiran Pangal ,  Balaji Srinivasan ,  Chaohong Hu

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C7/00 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/419 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

    Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.

    Abstract translation: 多级读取可以根据读取的存储器单元的阈值电压动态地改变字线电容。 多级读取可以减少电流尖峰，并减少读取期间存储单元的加热。 存储器件包括用于将所选择的存储器单元的字线连接到感测电路的全局字线驱动器，以及存储器单元本地的本地字线驱动器。 在字线被充电到读取电压之后，控制逻辑可以选择性地启用和禁用全局字线驱动器和本地字线驱动器的一部分或全部，同时将不同的离散电压电平应用于位线以执行多级读取。

    PHASE CHANGE MEMORY CURRENT
    2.
    发明申请
    PHASE CHANGE MEMORY CURRENT 有权
    相变记忆电流

    公开(公告)号：US20160351258A1

    公开(公告)日：2016-12-01

    申请号：US14725826

    申请日：2015-05-29

    Applicant: Intel Corporation

    Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal ,  Raymond W. Zeng

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79

    Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

    Abstract translation: 本公开涉及相变存储器电流。 一种装置包括一个包括字线（WL）控制模块和位线（BL）控制模块的存储器控​​制器，该存储器控制器开始选择一个存储单元。 该装置还包括缓解模块，用于配置第一线路选择逻辑以减少存储器单元的瞬态能量耗散，与选择存储器单元有关的瞬态能量。

    Cross point memory control
    4.
    发明授权
    Cross point memory control 有权

    公开(公告)号：US10546634B2

    公开(公告)日：2020-01-28

    申请号：US16140441

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Raymond W. Zeng ,  Mase J. Taub ,  Kiran Pangal ,  Sandeep K. Guliani

    IPC: G11C13/00 ,  G11C8/06 ,  G11C16/08 ,  G11C16/34

    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

    Cross point memory control
    5.
    发明授权
    Cross point memory control 有权

    公开(公告)号：US10134468B2

    公开(公告)日：2018-11-20

    申请号：US15465470

    申请日：2017-03-21

    Applicant: Intel Corporation

    Inventor： Raymond W. Zeng ,  Mase J. Taub ,  Kiran Pangal ,  Sandeep K. Guliani

    IPC: G11C13/00

    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

    RESET CURRENT DELIVERY IN NON-VOLATILE RANDOM ACCESS MEMORY
    8.
    发明申请
    RESET CURRENT DELIVERY IN NON-VOLATILE RANDOM ACCESS MEMORY 有权
    在非易失性随机访问存储器中复位电流传输

    公开(公告)号：US20160358652A1

    公开(公告)日：2016-12-08

    申请号：US14731212

    申请日：2015-06-04

    Applicant: Intel Corporation

    Inventor： Sandeep K. Guliani ,  Ved Pragyan

    IPC: G11C13/00 ,  G06F12/08

    CPC classification number: G11C13/0097 ,  G06F12/0891 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/76

    Abstract: Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了用于向诸如相变存储器（PCM）设备的非易失性随机存取存储器（NVRAM）提供复位电流的技术和配置。 在一个实施例中，该装置可以包括NVRAM装置; 与NVRAM器件耦合以将选择镜电压施加到NVRAM器件的选择镜电路，以选择NVRAM器件的存储器单元; 以及与NVRAM器件耦合的复位镜电路，以在施加选择镜电压之后将复位镜电压施加到NVRAM器件的存储单元，以复位存储器单元。 复位镜电压可以低于选择镜电压，以便于将高于电流阈值的复位电流传送到存储器单元。 可以描述和/或要求保护其他实施例。

    Cross-point memory bias scheme
    9.
    发明授权
    Cross-point memory bias scheme 有权
    交叉点记忆偏差方案

    公开(公告)号：US09224465B2

    公开(公告)日：2015-12-29

    申请号：US14221572

    申请日：2014-03-21

    Applicant: Intel Corporation

    Inventor： Nathan R. Franklin ,  Sandeep K. Guliani ,  Mase J. Taub ,  Kiran Pangal

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C2213/76

    Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

    Abstract translation: 本公开涉及一种交叉点存储器偏置方案。 一种装置，包括：存储器控制器，包括字线（WL）控制模块和位线控制模块，所述存储器控制器被配置为启动目标存储器单元的选择; 感测模块​​，其被配置为确定所述目标存储器单元是否已被选择; 以及配置为如果所述目标单元未被选择则建立C单元偏压的C单元偏置模块。

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