公开(公告)号：US20170139864A1

公开(公告)日：2017-05-18

申请号：US15419443

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

公开(公告)号：US20160092393A1

公开(公告)日：2016-03-31

申请号：US14497925

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

Abstract translation: 一些实施例包括具有耦合到串行总线的节点的装置和方法，以及控制器，以向第一电路路径和第二电路路径之一提供控制信号，以便改变位于第一电路路径和第二电路路径之间的节点处的信号的电终端 在控制器的第一模式期间通过第一电路路径进行第一电终接，并且在控制器的第二模式期间通过第二电路路径进行第二电终接。 控制器可以被布置为在第一和第二模式期间向第一和第二电路路径提供控制信号，而不在第一和第二模式期间从控制器向第一和第二电路路径提供另一个控制信号。

公开(公告)号：US09916272B2

公开(公告)日：2018-03-13

申请号：US15419443

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

公开(公告)号：US10204068B2

公开(公告)日：2019-02-12

申请号：US15901351

申请日：2018-02-21

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

公开(公告)号：US20180181515A1

公开(公告)日：2018-06-28

申请号：US15901351

申请日：2018-02-21

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

公开(公告)号：US12007828B2

公开(公告)日：2024-06-11

申请号：US17628886

申请日：2020-08-03

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Mallari Hanchate ,  Sayan Lahiri ,  Vijayakumar Dibbad

IPC: G06F1/3293 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06F1/3293 ,  G06F9/5094 ,  G06T1/20

Abstract: A switchable graphics management scheme, which uses performance/watt information of both the iGPU/dGPU along with system real-time resources like SoC (system-on-chip) thermal, system power budgets to decide on the right GPU for rendering tasks. The scheme uses this threshold power point information along with system resources to determine the optimized GPU for tasks rendering for all applications and use cases. As such, the scheme of adapts to each system design based on capabilities of that specific system.

公开(公告)号：US09558144B2

公开(公告)日：2017-01-31

申请号：US14497925

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F3/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

Abstract translation: 一些实施例包括具有耦合到串行总线的节点的装置和方法，以及控制器，以向第一电路路径和第二电路路径之一提供控制信号，以便改变位于第一电路路径和第二电路路径之间的节点处的信号的电终端 在控制器的第一模式期间通过第一电路路径进行第一电终接，并且在控制器的第二模式期间通过第二电路路径进行第二电终接。 控制器可以被布置为在第一和第二模式期间向第一和第二电路路径提供控制信号，而不在第一和第二模式期间从控制器向第一和第二电路路径提供另一个控制信号。