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公开(公告)号:US20240273028A1
公开(公告)日:2024-08-15
申请号:US18600496
申请日:2024-03-08
申请人: Intel Corporation
发明人: Corey D. GOUGH , Yuval BUSTAN , Arvind RAMAN , Mariusz ORIOL , Nilanjan PALIT , Philip ABRAHAM , Priyanka GANESH , Daniel G. CARTAGENA , Mateusz DUCHALSKI
IPC分类号: G06F12/0842 , G06F1/3206 , G06F1/3293 , G06F12/084
CPC分类号: G06F12/0842 , G06F1/3206 , G06F1/3293 , G06F12/084
摘要: Examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. The circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. The energy usage of the process can be based on dynamic capacitance (Cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.
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公开(公告)号:US11892710B2
公开(公告)日:2024-02-06
申请号:US17894144
申请日:2022-08-23
CPC分类号: G02C11/10 , G02C7/02 , G06F1/163 , G06F1/3293 , G06V40/1306 , G06V40/1347 , G06V40/1365 , G06V40/1376
摘要: A system comprises an eyewear device that includes a frame, a temple connected to a lateral side of the frame, a fingerprint sensor, and a sensing circuit. The fingerprint sensor includes an input surface to receive input of a finger skin surface. The sensing circuit is configured to track a pattern of fingerprint ridges of the finger skin surface on the input surface. Execution of programming by a processor configures the system to perform functions to track, via the sensing circuit, the pattern of fingerprint ridges of the finger skin surface on the input surface; generate a fingerprint image having the tracked pattern of fingerprint ridges; extract fingerprint features from the fingerprint image; and authorize the user to utilize the eyewear device based on the extracted fingerprint features.
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公开(公告)号:US11880714B2
公开(公告)日:2024-01-23
申请号:US17521592
申请日:2021-11-08
申请人: Intel Corporation
CPC分类号: G06F9/5027 , G06F1/26 , G06F1/3293 , G06F9/45558 , G06F9/48 , G06F9/485 , G06F9/4806 , G06F9/4843 , G06F9/4856 , G06F9/4881 , G06F9/4893 , G06F9/50 , G06F9/5005 , G06F9/505 , G06F9/5044 , G06F9/5055 , G06F9/5061 , G06F9/5072 , G06F9/5094 , G06F9/54 , G06F9/547 , G06F2009/45595
摘要: Technologies for providing dynamic selection of edge and local accelerator resources includes a device having circuitry to identify a function of an application to be accelerated, determine one or more properties of an accelerator resource available at the edge of a network where the device is located, and determine one or more properties of an accelerator resource available in the device. Additionally, the circuitry is to determine a set of acceleration selection factors associated with the function, wherein the acceleration factors are indicative of one or more objectives to be satisfied in the acceleration of the function. Further, the circuitry is to select, as a function of the one or more properties of the accelerator resource available at the edge, the one or more properties of the accelerator resource available in the device, and the acceleration selection factors, one or more of the accelerator resources to accelerate the function.
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公开(公告)号:US11815980B2
公开(公告)日:2023-11-14
申请号:US17721467
申请日:2022-04-15
发明人: Kimiyasu Mizuno , Tsuyoshi Minami , Shuhei Uchida , Munetaka Seo
IPC分类号: G06F1/3293 , G04G19/00 , G06F1/3234
CPC分类号: G06F1/3293 , G04G19/00 , G06F1/3265
摘要: An electronic device includes a memory; a first processor; a second processor for which power consumption is lower than power consumption of the first processor; a communicator that communicates with an external device; and a switch that switches a connection destination of the communicator to the first processor or the second processor. The second processor is configured to, in a case in which a condition for transitioning to a power suppression state that is an operating state in which power consumption is suppressed is satisfied, connect the communicator by the switch. The first processor is configured to, in a case in which a condition for transitioning to a normal state that is a normal operating state is satisfied, connect the communicator by the switch.
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公开(公告)号:US11748606B2
公开(公告)日:2023-09-05
申请号:US17317857
申请日:2021-05-11
申请人: INTEL CORPORATION
发明人: Kamal Sinha , Balaji Vembu , Eriko Nurvitadhi , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Farshad Akhbari , Narayan Srinivasa , Feng Chen , Dukhwan Kim , Nadathur Rajagopalan Satish , John C. Weast , Mike B. MacPherson , Linda L. Hurd , Vasanth Ranganathan , Sanjeev S. Jahagirdar
IPC分类号: G06F7/50 , G06N3/063 , G06N3/08 , G06N3/04 , G06T1/20 , G06F9/30 , G06T15/00 , G06F15/78 , G06F15/76 , G06F1/3287 , G06F1/3293 , G06N3/084 , G06N3/044 , G06N3/045 , G06T1/60
CPC分类号: G06N3/063 , G06F1/3287 , G06F1/3293 , G06F9/30014 , G06F9/30036 , G06F15/76 , G06F15/78 , G06N3/04 , G06N3/044 , G06N3/045 , G06N3/08 , G06N3/084 , G06T1/20 , G06T15/005 , G06T1/60
摘要: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20230195519A1
公开(公告)日:2023-06-22
申请号:US17559352
申请日:2021-12-22
申请人: Intel Corporation
CPC分类号: G06F9/4893 , G06T1/20 , G06T1/60 , G06N20/00 , G06F1/3293 , G06F9/505
摘要: One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.
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公开(公告)号:US11675416B2
公开(公告)日:2023-06-13
申请号:US17659566
申请日:2022-04-18
申请人: Apple Inc.
发明人: Shah M. Sharif
IPC分类号: G06F1/3293 , G06F1/3287 , G11C5/14
CPC分类号: G06F1/3293 , G06F1/3287 , G11C5/147
摘要: A cross-domain power control circuit is disclosed. The circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.
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公开(公告)号:US20230145708A1
公开(公告)日:2023-05-11
申请号:US18096098
申请日:2023-01-12
发明人: Brandon Gruber
IPC分类号: G06F1/3293 , G06F9/4401
CPC分类号: G06F1/3293 , G06F9/4418
摘要: Methods and apparatus for performing timed functions in battery-powered, wireless electronic devices, such as sensors or control modules. Such electronic devices comprise a main processor and a co-processor. When the main processor enters a quiescent state in order to preserve battery life, one or more timed functions are transferred from the main processor to the co-processor just before the main processor enters the quiescent state. When the co-processor determines that it is time to perform the timed function, the co-processor wakes the main processor in order for the main processor to perform the timed function.
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公开(公告)号:US20190250925A1
公开(公告)日:2019-08-15
申请号:US16290566
申请日:2019-03-01
申请人: Apple Inc.
发明人: Hardik K. Doshi
IPC分类号: G06F9/4401 , G06F1/3293 , G06F1/3287 , G06F1/3203
CPC分类号: G06F9/4405 , G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F9/4418 , G06F9/442 , Y02D10/122 , Y02D10/171
摘要: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.
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公开(公告)号:US20190250691A1
公开(公告)日:2019-08-15
申请号:US16107970
申请日:2018-08-21
发明人: KYUNGSOO LEE , TAEKKYUN SHIN
CPC分类号: G06F1/324 , G06F1/3293 , G06N3/02 , G06N20/00
摘要: A context hub receives and processes data from multiple sensors. An operation method of the context hub includes identifying a pattern of context data input to the context hub from at least one of the sensors, determining a dynamic voltage-frequency scaling (DVFS) level corresponding to the identified pattern of the context data, and processing, at the context hub, the context data by using a clock signal or a driving voltage corresponding to the determined DVFS level.
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