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    CLOUD STORAGE ACCELERATION LAYER FOR ZONED NAMESPACE DRIVES
    1.
    发明申请
    CLOUD STORAGE ACCELERATION LAYER FOR ZONED NAMESPACE DRIVES 有权

    公开(公告)号：US20230051328A1

    公开(公告)日：2023-02-16

    申请号：US17819435

    申请日：2022-08-12

    Applicant: Intel Corporation

    Inventor： Mariusz Barczak ,  Wojciech Malikowski ,  Mateusz Kozlowski ,  Lukasz Lasek ,  Artur Paszkiewicz ,  Kapil Karkra

    IPC: G06F12/10

    Abstract: Systems, apparatuses, and methods provide for a memory controller to manage a tiered memory including a zoned namespace drive memory capacity tier. For example, a memory controller includes logic to translate a standard zoned namespace drive address associated with a user write to a tiered memory address write. The tiered memory address write is associated with the tiered memory including the persistent memory cache tier and the zoned namespace drive memory capacity tier. A plurality of tiered memory address writes are collected, where the plurality of tiered memory address writes include the tiered memory address write and other tiered memory address writes in the persistent memory cache tier. The collected plurality of tiered memory address writes are transferred from the persistent memory cache tier to the zoned namespace drive memory capacity tier, via an append-type zoned namespace drive write command.

    Non-volatile memory cloning with hardware copy-on-write support
    3.
    发明授权
    Non-volatile memory cloning with hardware copy-on-write support 有权

    公开(公告)号：US10725690B2

    公开(公告)日：2020-07-28

    申请号：US15984138

    申请日：2018-05-18

    Applicant: Intel Corporation

    Inventor： Jakub Radtke ,  Wojciech Malikowski ,  Tobiasz Domagala

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: Examples may include a non-volatile memory having a memory including a first table of device physical addresses and a second table of physical device addresses; a control register to receive a clone command to clone a second memory region of the memory as a copy of a first memory region of the memory, the first and second memory regions being referenced by different device physical addresses; and address translation logic, upon receipt of the clone command, create a first entry in the first table for each page of the first memory region and create a second entry in the first table for each page of the second memory region, each first table entry for the first memory region and each first table entry for the second memory region pointing to a same entry in the second table.

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