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公开(公告)号:US20190042409A1
公开(公告)日:2019-02-07
申请号:US15995213
申请日:2018-06-01
Applicant: Intel Corporation
Inventor: Grzegorz Jereczek , Pawel Lebioda , Maciej Maciejewski , Pawel Makowski , Piotr Pelplinski , Jakub Radtke , Aleksandra Wisz
IPC: G06F12/06 , G06F12/0862 , G06F9/30
Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
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公开(公告)号:US10552319B2
公开(公告)日:2020-02-04
申请号:US15995213
申请日:2018-06-01
Applicant: Intel Corporation
Inventor: Grzegorz Jereczek , Pawel Lebioda , Maciej Maciejewski , Pawel Makowski , Piotr Pelplinski , Jakub Radtke , Aleksandra Wisz
Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
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公开(公告)号:US10725690B2
公开(公告)日:2020-07-28
申请号:US15984138
申请日:2018-05-18
Applicant: Intel Corporation
Inventor: Jakub Radtke , Wojciech Malikowski , Tobiasz Domagala
IPC: G06F3/06 , G06F12/1009
Abstract: Examples may include a non-volatile memory having a memory including a first table of device physical addresses and a second table of physical device addresses; a control register to receive a clone command to clone a second memory region of the memory as a copy of a first memory region of the memory, the first and second memory regions being referenced by different device physical addresses; and address translation logic, upon receipt of the clone command, create a first entry in the first table for each page of the first memory region and create a second entry in the first table for each page of the second memory region, each first table entry for the first memory region and each first table entry for the second memory region pointing to a same entry in the second table.
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公开(公告)号:US10691506B2
公开(公告)日:2020-06-23
申请号:US16236162
申请日:2018-12-28
Applicant: INTEL CORPORATION
Inventor: Grzegorz Jereczek , Jakub Radtke , Pawel Makowski , Maciej Maciejewski , Pawel Lebioda , Piotr Pelplinski , Aleksandra Wisz
IPC: G06F16/23 , G06F9/52 , G06F9/50 , H04L9/06 , G06F16/907 , G06F16/182
Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.
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公开(公告)号:US20190096489A1
公开(公告)日:2019-03-28
申请号:US15718090
申请日:2017-09-28
Applicant: Intel Corporation
Inventor: Stanislaw Mosiolek , Jakub Radtke
Abstract: A non-volatile memory module and a read-only operation of the non-volatile memory module are disclosed. A non-volatile memory module such as a non-volatile dual in-line memory module (NVDIMM) may, in response to a command from a host, set a particular memory range of the memory module as a read-only state by storing an address of the memory range with a secret associated with the memory range in an internal database of the memory module. The memory module may then reject a write command to the memory range in the read-only state. The internal database is stored within the memory module and the write protection is implemented inside the memory module so that no external entity may change the protected memory region.
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