公开(公告)号：US20190042409A1

公开(公告)日：2019-02-07

申请号：US15995213

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Grzegorz Jereczek ,  Pawel Lebioda ,  Maciej Maciejewski ,  Pawel Makowski ,  Piotr Pelplinski ,  Jakub Radtke ,  Aleksandra Wisz

IPC: G06F12/06 ,  G06F12/0862 ,  G06F9/30

Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.

公开(公告)号：US10552319B2

公开(公告)日：2020-02-04

申请号：US15995213

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Grzegorz Jereczek ,  Pawel Lebioda ,  Maciej Maciejewski ,  Pawel Makowski ,  Piotr Pelplinski ,  Jakub Radtke ,  Aleksandra Wisz

IPC: G06F12/00 ,  G06F12/06 ,  G06F9/30 ,  G06F12/0862 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10

Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.

公开(公告)号：US10282287B2

公开(公告)日：2019-05-07

申请号：US14981800

申请日：2015-12-28

Applicant: Intel Corporation

Inventor： Wojciech Malikowski ,  Maciej Maciejewski

IPC: G06F3/06 ,  G06F12/02

Abstract: Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of allocating direct access mode (DAM) space across interleaved non-volatile memory (NVM) modules are disclosed and described.

公开(公告)号：US10691506B2

公开(公告)日：2020-06-23

申请号：US16236162

申请日：2018-12-28

Applicant: INTEL CORPORATION

Inventor： Grzegorz Jereczek ,  Jakub Radtke ,  Pawel Makowski ,  Maciej Maciejewski ,  Pawel Lebioda ,  Piotr Pelplinski ,  Aleksandra Wisz

IPC: G06F16/23 ,  G06F9/52 ,  G06F9/50 ,  H04L9/06 ,  G06F16/907 ,  G06F16/182

Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.

公开(公告)号：US20170185293A1

公开(公告)日：2017-06-29

申请号：US14981800

申请日：2015-12-28

Applicant: Intel Corporation

Inventor： Wojciech Malikowski ,  Maciej Maciejewski

IPC: G06F3/06

CPC classification number: G06F12/0246

Abstract: Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of allocating direct access mode (DAM) space across interleaved non-volatile memory (NVM) modules are disclosed and described.