公开(公告)号：US20230062210A1

公开(公告)日：2023-03-02

申请号：US17460524

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Yang-Chun Cheng ,  Dax M. Crum

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8234

Abstract: Techniques are provided herein to form semiconductor devices having different work function metals over different devices. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to gate-all-around (GAA) transistors. In an example, neighboring semiconductor devices each include a different work function to act as the device gate electrode for each semiconductor device. More specifically, a first semiconductor device may be a p-channel GAA transistor with a first work function metal around the various nanoribbons of the transistor, while the second neighboring semiconductor device may be an n-channel GAA transistor with a second work function metal around the various nanoribbons of the transistor. No portions of the first work function metal are present around the nanoribbons of the second semiconductor device and no portions of the second work function metal are present around the nanoribbons of the first semiconductor device.

公开(公告)号：US20230057326A1

公开(公告)日：2023-02-23

申请号：US17406480

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Anand S. Murthy ,  Yang-Chun Cheng ,  Ryan Pearce ,  Guillaume Bouche

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.

公开(公告)号：US20230032866A1

公开(公告)日：2023-02-02

申请号：US17443714

申请日：2021-07-27

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Yang-Chun Cheng ,  Shaestagir Chowdhury ,  Guillaume Bouche

IPC: H01L23/528 ,  H01L29/417

Abstract: Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.