公开(公告)号：US20230057326A1

公开(公告)日：2023-02-23

申请号：US17406480

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Anand S. Murthy ,  Yang-Chun Cheng ,  Ryan Pearce ,  Guillaume Bouche

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.

公开(公告)号：US12230714B2

公开(公告)日：2025-02-18

申请号：US18622615

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Ritesh K. Das ,  Kiran Chikkadi ,  Ryan Pearce

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/02

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US20220199458A1

公开(公告)日：2022-06-23

申请号：US17127860

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Michael Makowski ,  Sudipto Naskar ,  Ryan Pearce ,  Nita Chandrasekhar ,  Minyoung Lee ,  Christopher Parker

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

公开(公告)号：US12224349B2

公开(公告)日：2025-02-11

申请号：US16868828

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： Ritesh K. Das ,  Kiran Chikkadi ,  Ryan Pearce

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US20250113600A1

公开(公告)日：2025-04-03

申请号：US18477947

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Yulia Gotlib ,  Matthew J. Prince ,  Sachin S. Vaidya ,  Ying Zhou ,  Xiaoye Qin ,  Ryan Pearce ,  Andrew Arnold ,  Chiao-Ti Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.

公开(公告)号：US12087614B2

公开(公告)日：2024-09-10

申请号：US17127860

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Michael Makowski ,  Sudipto Naskar ,  Ryan Pearce ,  Nita Chandrasekhar ,  Minyoung Lee ,  Christopher Parker

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

公开(公告)号：US20200211833A1

公开(公告)日：2020-07-02

申请号：US16632449

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Ryan Pearce ,  Sudipto Naskar ,  Nita Chandrasekhar ,  Minyoung Lee ,  Harinath Reddy ,  Christopher G. Parker

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/762

Abstract: An integrated circuit device includes: a semiconductor structure having a high aspect ratio (HAR) feature, the HAR feature having a depth of between 25 nanometers (nm) and 250 nm, a width of between 5 nm and 50 nm, and a depth-to-width aspect ratio of 5:1 or more; and a gap-fill material at least partially filling the HAR feature, the gap-fill material including silicon and nitrogen and being substantially free of a seam located between opposing sides of the HAR feature. A semiconductor process platform includes a nitrogen radical generator to generate nitrogen radicals for delivery to one of the zones, each zone being configured to deliver a separate precursor of a deposition cycle. A method of semiconductor device fabrication includes reacting surfaces of the HAR feature with a silicon precursor, and reacting the silicon-precursed surfaces with nitrogen plasma to form a monolayer of silicon nitride.