公开(公告)号：US20150371949A1

公开(公告)日：2015-12-24

申请号：US14841018

申请日：2015-08-31

Applicant: INTEL CORPORATION

Inventor： Daniel J. Zierath ,  Shaestagir Chowdhury ,  Chi-Hwa Tsang

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Abstract translation: 公开了能够通过无电解材料沉积技术形成的互连，通孔，金属栅极和其它导电特征的技术。 在一些实施方案中，该技术采用无电填料结合无电成核材料（ENM）和无电压抑制材料（ESM）之间的高生长速率选择性，以产生这些特征的自下而上或其他期望的填充图案。 合适的ENM可能存在于底层或其他现有结构中，或可提供。 ESM的设置是为了防止或以其他方式抑制ESM覆盖的特征区域的成核，这又防止或以其他方式减缓这些区域的无电生长速率。 因此，ENM场地的无电增长率高于ESM站点上的无电增长率。

公开(公告)号：US20230102711A1

公开(公告)日：2023-03-30

申请号：US17485151

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ming-Yi Shen ,  Nita Chandrasekhar ,  Blake Bluestein ,  Tiffany Zink ,  Shaestagir Chowdhury

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

公开(公告)号：US20230032866A1

公开(公告)日：2023-02-02

申请号：US17443714

申请日：2021-07-27

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Yang-Chun Cheng ,  Shaestagir Chowdhury ,  Guillaume Bouche

IPC: H01L23/528 ,  H01L29/417

Abstract: Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.

公开(公告)号：US11443983B2

公开(公告)日：2022-09-13

申请号：US16139241

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Shaestagir Chowdhury ,  Sirikarn Surawanvijit ,  Biswadeep Saha ,  Erica J. Thompson

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  C22C19/03 ,  C22C19/07 ,  H01L23/522 ,  C09K13/00

Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.