公开(公告)号：US20240237193A1

公开(公告)日：2024-07-11

申请号：US18618075

申请日：2024-03-27

Applicant: Intel Corporation

Inventor： Yi HUANG ,  Xiaoning YE ,  Kai XIAO ,  James A. McCALL ,  Yanjie ZHU

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0253 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/10189

Abstract: An apparatus is described. The apparatus includes a memory module. The memory module includes a first printed circuit board having a first transmission line. The first printed circuit board has memory chips disposed thereon. The memory module includes a second printed board having a second transmission line that is coupled to the first transmission line to form a signal path through the first and second printed circuit boards. The second printed circuit board has greater flexibility than the first printed circuit board. The memory module includes a connector to align an I/O that is coupled to the second transmission line with a corresponding I/O that is associated with a motherboard that is to send and/or receive a signal to and/or from the signal path.

公开(公告)号：US20250141134A1

公开(公告)日：2025-05-01

申请号：US19004170

申请日：2024-12-27

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL ,  Yanjie ZHU

IPC: H01R12/72 ,  H01R13/02 ,  H05K1/18

Abstract: A multi-slot connector having reduced DIMM-to-DIMM pitch distances can support up to 64 memory channels for next generation DDR (double data rate) technology, including DDR6. To support the increase in memory channels, while compensating for limited form factor motherboards, the multi-slot connector includes two or more slots for devices, such as DIMMs, to connect to a motherboard or other platform. Reduced pitch distances between the DIMMs, shortened connector pins, thinner contacts, and complementary reduced pitch distances in a ball grid array (BGA) used to connect to the motherboard or other platform, provides a compact multi-slot connector that can support up to 64 memory channels with improved performance characteristics. An optional cooling device can be employed between the slots as needed to maintain optimal performance.

公开(公告)号：US20210279128A1

公开(公告)日：2021-09-09

申请号：US17327432

申请日：2021-05-21

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Bill NALE ,  Zibing YANG ,  Yanjie ZHU

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

Abstract: A method is described. The method includes a buffer semiconductor chip receiving a plurality of data signals. The method includes the buffer chip calculating first CRC information from the plurality of data signals. The method includes the buffer chip transmitting the plurality of data signals in parallel with the first CRC information if a read burst transfer sequence is being performed, the buffer chip receiving second CRC information in parallel with the plurality of data signals and comparing the first CRC information with the second CRC information if a write burst transfer sequence is being performed.