公开(公告)号：US20220418090A1

公开(公告)日：2022-12-29

申请号：US17897043

申请日：2022-08-26

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H05K1/02 ,  H01R12/72 ,  H01R12/73 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10

Abstract: Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers, first and second conductive connections, first and second trace portions, first, second, and third routings, and a via wherein: the first conductive connection is coupled to the first trace portion, the second conductive connection is coupled to the second trace portion, the first routing is formed in a first layer of the plurality of layers, the second routing is formed in a second layer of the plurality of layers, the third routing is formed in the first layer of the plurality of layers, a portion of the first routing overlaps with a portion of the second routing to provide a capacitive region, and the via conductively couples a portion of the second routing overlaps with a portion of the third routing.

公开(公告)号：US20220304142A1

公开(公告)日：2022-09-22

申请号：US17831774

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Xiang LI ,  Landon HANKS ,  George VERGIS ,  James A. McCALL

IPC: H05K1/02 ,  H05K3/46

Abstract: Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers and at least one conductive connection. In some examples, the at least one conductive connection is connected to a layer of the plurality of layers. In some examples, at least one layer of the plurality of layers comprises a conductive material. In some examples, the at least two layers of the plurality of layers comprise conductive material that extend in an axis towards the at least one conductive connection but do not overlap with the at least one layer of the plurality of layers comprising the conductive material.

公开(公告)号：US20190042162A1

公开(公告)日：2019-02-07

申请号：US16104040

申请日：2018-08-16

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Suneeta SAH ,  George VERGIS ,  Dimitrios ZIAKAS ,  Bill NALE ,  Chong J. ZHAO ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.

公开(公告)号：US20180373665A1

公开(公告)日：2018-12-27

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin LI ,  Changhong LIN ,  James A. McCALL ,  Harry MULJONO

IPC: G06F13/40 ,  H04B3/23 ,  G06F13/16 ,  G11C7/12 ,  G11C7/22

CPC classification number: G06F13/4072 ,  G06F13/1689 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  H04B3/231

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuity to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

公开(公告)号：US20220393682A1

公开(公告)日：2022-12-08

申请号：US17890500

申请日：2022-08-18

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Kuljit S. BAINS ,  Christopher P. MOZAK

IPC: H03K19/0175 ,  G06F13/40 ,  G06F13/42 ,  G11C7/22

Abstract: A system has an unmatched communication architecture for a unidirectional command bus and compensates for drift on the command bus based on data provided on a bidirectional data bus. The memory device has an oscillator to measure drift or an amount of delay for the command bus over a time interval. The memory device can return a value over the data bus to the memory controller based on the delay measured with the oscillator. Based on receiving the value, the memory controller can adjust configuration settings for communication on the command bus.

公开(公告)号：US20190102331A1

公开(公告)日：2019-04-04

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang LI ,  Yunhui CHU ,  Jun LIAO ,  George VERGIS ,  James A. McCALL ,  Charles C. PHARES ,  Konika GANGULY ,  Qin LI

IPC: G06F13/16 ,  G11C5/06 ,  G11C5/04 ,  G06F1/18 ,  H01R12/73

CPC classification number: G06F13/1694 ,  G06F1/185 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  H01R12/73

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US20190042499A1

公开(公告)日：2019-02-07

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

公开(公告)号：US20190042095A1

公开(公告)日：2019-02-07

申请号：US16111156

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： George VERGIS ,  Bill NALE ,  Derek A. THOMPSON ,  James A. McCALL ,  Rajat AGARWAL ,  Wei P. CHEN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a memory controller having register space to inform the memory controller that the memory controller is coupled to a memory module that conforms to a first memory chip industry standard specification but is composed of memory chips that conform to a second, different memory chip industry standard specification.

公开(公告)号：US20170329727A1

公开(公告)日：2017-11-16

申请号：US15608846

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Christopher P. MOZAK ,  James A. McCALL ,  Bryan K. CASPER

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1657 ,  G06F11/10 ,  G06F13/4004 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4217 ,  G06F13/4221 ,  G06F13/4234 ,  H04L25/4915 ,  Y02D10/14 ,  Y02D10/151

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US20230214669A1

公开(公告)日：2023-07-06

申请号：US18120848

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Wenzhi WANG ,  Yunhui CHU ,  James A. McCALL ,  Chunfei YE ,  Tonia M. ROSE ,  Caroline GRIMES

IPC: G06N5/01 ,  H03K19/00

CPC classification number: G06N5/01 ,  H03K19/0005

Abstract: Decision feedback equalization (DFE) training time in a memory device is reduced through the use of a hybrid search to select values of tap coefficients for taps in the DFE. The hybrid search includes two searches. A first search is performed to identify initial values of tap coefficients, a second search uses the initial values of tap coefficients to find the final values of tap coefficients.