公开(公告)号：US20210050512A1

公开(公告)日：2021-02-18

申请号：US17041882

申请日：2018-05-31

Applicant: Intel Corporation

Inventor： Davide Fugazza ,  Stephen Russell ,  Yao Jin ,  Andrea Redaelli ,  Pengyuan Zheng ,  Yongiun J. Hu

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A phase change memory (PCM) cell (100) includes a PCM layer (105), a metal ceramic composite material layer (120), and a carbon nitride (CNX) electrode layer (110) disposed between the PCM material layer and the metal ceramic composite material layer. The CNX electrode layer can have an electrical resistivity at room temperature of from about 1 mOhm-cm to about 2000 mOhm-cm and an electrical resistivity at 650° C. of from about 1 mOhm-cm to about 100 mOhm-cm.

公开(公告)号：US11093414B2

公开(公告)日：2021-08-17

申请号：US16326116

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Yao Jin ,  Ashok Raj ,  Anthony E. G. Luck

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0811 ,  G06F11/30 ,  G06F11/34 ,  G06F13/14 ,  G06F12/0806 ,  G06F12/0842 ,  G06F3/06 ,  G06F13/40

Abstract: A computing system includes a plurality of nodes including a first node, the first node including at least one core, a memory controller, a node-track register (MSR), and a monitoring counter array including a plurality of counters. The memory controller is to access a plurality of bits of the node-track MSR to determine a subset of nodes to be tracked, wherein the subset of nodes includes the first node and a second node. The memory controller is further to allocate a first counter of the plurality of counters to track memory requests sent to a local system memory by the first node; and allocate a second counter of the plurality of counters to track a memory response associated with a memory request sent by the first node to the second node.