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1.发明申请Second-Order Polynomial, Interpolation-Based, Sampling Rate Converter and Method and Transmitters Employing the Same 审中-公开二阶多项式，基于插值的采样率转换器及其使用的方法和发送器公开(公告)号：US20080309524A1
公开(公告)日：2008-12-18
申请号：US12121090
申请日：2008-05-15
IPC分类号： H03M7/00
CPC分类号： H03H17/0685 , H03H17/028
摘要： A sampling rate converter, a method of performing digital sampling rate conversion and a wireless transmitter incorporating the filter or the method. In one embodiment, the sampling rate converter includes: (1) an input configured to receive digital data from a first clock domain sampled at a first sampling rate, (2) an output configured to provide digital data to a second clock domain sampled at a second sampling rate that differs from the first sampling rate and (3) a filter with a second-order, polynomial-based impulse response coupled to the input and the output and configured to apply coefficients having only one nonunitary divisor to the digital data from the first clock domain.
摘要翻译： 采样率转换器，执行数字采样率转换的方法和包含滤波器或方法的无线发射器。 在一个实施例中，采样率转换器包括：（1）被配置为从以第一采样率采样的第一时钟域接收数字数据的输入，（2）被配置为将数字数据提供给在 第二采样率与第一采样率不同，以及（3）具有耦合到输入和输出的二阶多项式的脉冲响应的滤波器，并且被配置为将仅具有一个非维数除数的系数应用于来自 第一个时钟域
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2.发明授权Digital phase-locked loop with wide capture range, low phase noise, and reduced spurs 失效数字锁相环具有宽捕捉范围，低相位噪声和减少杂散公开(公告)号：US08686771B2
公开(公告)日：2014-04-01
申请号：US13485413
申请日：2012-05-31
申请人： Emmanouil Frantzeskakis , Ioannis L. Syllaios , Georgios Sfikas , Henrik Jensen , Stephen Wu , Padmanava Sen
发明人： Emmanouil Frantzeskakis , Ioannis L. Syllaios , Georgios Sfikas , Henrik Jensen , Stephen Wu , Padmanava Sen
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/1976 , H03L2207/50
摘要： The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.
摘要翻译： 本公开涉及用于建立和维持所生成的输出信号和参考输入信号之间的相位关系的数字锁相环（DPLL）和混合锁相环（HPLL）。 DPLL使用基于计数器的循环来初始将DPLL锁定。 此后，DPLL禁用基于计数器的循环并切换到具有多模式分频器（MMD）的回路。 DPLL可以实现消除技术，以减少由MMD引入的相位噪声。 HPLL还包括一个带有MMD的循环。 HPLL可以实现类似的消除技术，以减少由MMD引入的相位噪声。
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