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    Thyristor-based SRAM and method for the fabrication thereof
    4.
    发明授权
    Thyristor-based SRAM and method for the fabrication thereof 失效
    基于晶闸管的SRAM及其制造方法

    公开(公告)号：US06849481B1

    公开(公告)日：2005-02-01

    申请号：US10628912

    申请日：2003-07-28

    申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zhen Zheng ,  Tommy Lai ,  Weining Li

    发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zhen Zheng ,  Tommy Lai ,  Weining Li

    IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： H01L29/66393 ,  H01L27/11

    摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

    摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

    Horizontal tram
    5.
    发明授权
    Horizontal tram 有权
    水平电车

    公开(公告)号：US07183590B2

    公开(公告)日：2007-02-27

    申请号：US11422560

    申请日：2006-06-06

    申请人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

    发明人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

    IPC分类号： H01L29/74

    CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

    摘要： An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

    摘要翻译： 集成电路结构包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。

    Thyristor-based SRAM
    6.
    发明授权
    Thyristor-based SRAM 有权
    基于晶闸管的SRAM

    公开(公告)号：US07148522B2

    公开(公告)日：2006-12-12

    申请号：US11009772

    申请日：2004-12-11

    申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zhen Zheng ,  Tommy Lai ,  Weining Li

    发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zhen Zheng ,  Tommy Lai ,  Weining Li

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66393 ,  H01L27/11

    摘要： An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

    摘要翻译： 集成电路结构包括形成在其上的半导体衬底和晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

    Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof
    8.
    发明授权
    Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof 失效
    具有高电压氧化物的多电平门SONOS闪存器件及其制造方法

    公开(公告)号：US07015101B2

    公开(公告)日：2006-03-21

    申请号：US10683052

    申请日：2003-10-09

    申请人： Jia Zhen Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

    发明人： Jia Zhen Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

    摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

    摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成栅介质层。 栅极电介质层在半导体衬底上的多个器件区域中形成多个厚度。 在至少一个器件区域上形成第二介电层。 在第二电介质层的至少一部分上形成第三电介质层。 然后在第二介电层的部分中选择性地注入离子阱。

    Semiconductor local interconnect and contact
    9.
    发明授权
    Semiconductor local interconnect and contact 有权
    半导体局部互连和接触

    公开(公告)号：US07119005B2

    公开(公告)日：2006-10-10

    申请号：US11045202

    申请日：2005-01-27

    申请人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

    发明人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

    IPC分类号： H01L21/4763 ,  H01L21/336

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6656

    摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

    摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

    Semiconductor local interconnect and contact
    10.
    发明授权
    Semiconductor local interconnect and contact 有权
    半导体局部互连和接触

    公开(公告)号：US08304834B2

    公开(公告)日：2012-11-06

    申请号：US11466350

    申请日：2006-08-22

    申请人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

    发明人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

    IPC分类号： H01L27/12

    CPC分类号： H01L21/76895 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

    摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。