公开(公告)号：US06812529B2

公开(公告)日：2004-11-02

申请号：US09808864

申请日：2001-03-15

申请人： John D. Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd R. Abbott

发明人： John D. Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd R. Abbott

IPC分类号： H01L2949

CPC分类号： G11C11/412 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104

摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

公开(公告)号：US06962841B2

公开(公告)日：2005-11-08

申请号：US10659081

申请日：2003-09-10

申请人： John D. Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd R. Abbott

发明人： John D. Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd R. Abbott

IPC分类号： G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/412 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104

摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

公开(公告)号：US06599789B1

公开(公告)日：2003-07-29

申请号：US09713844

申请日：2000-11-15

申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

IPC分类号： H01L2184

CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。 源极/漏极区域形成在沟道区域的相对侧上。 绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。 形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。 半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。 半导体通道材料形成在空隙内。 相邻的源极/漏极区域横向靠近通道材料提供。 在通道材料上形成一个栅极。 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。

公开(公告)号：US06583518B2

公开(公告)日：2003-06-24

申请号：US09945380

申请日：2001-08-31

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Todd R. Abbott ,  Chih-Chen Cho

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Todd R. Abbott ,  Chih-Chen Cho

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

公开(公告)号：US06900494B2

公开(公告)日：2005-05-31

申请号：US10780014

申请日：2004-02-17

申请人： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

发明人： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

摘要翻译： 该方法包括在衬底之上形成由BPSG组成的层和多个晶体管，在BPSG层上形成电介质层，介电层由介电常数大于约6.0的材料构成，在该介电层中形成多个开口 电介质层和BPSG层，每个开口允许接触晶体管之一的掺杂区域，并且在每个开口中形成导电局部互连。 在另一实施例中，该方法包括在衬底之上和晶体管之间形成由BPSG组成的层，在形成在BPSG层中的开口中形成局部互连，在局部互连形成之后减小BPSG层的厚度，并形成 电介质层在BPSG层之上和局部互连之间，其中介电层具有大于约6.0的介电常数。

公开(公告)号：US06723597B2

公开(公告)日：2004-04-20

申请号：US10191833

申请日：2002-07-09

申请人： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

发明人： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming, a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

摘要翻译： 该方法包括在衬底之上形成由BPSG组成的层和多个晶体管，在BPSG层上形成电介质层，介电层由介电常数大于约6.0的材料构成，在该介电层中形成多个开口 电介质层和BPSG层，每个开口允许接触晶体管之一的掺杂区域，并且在每个开口中形成导电局部互连。 在另一个实施例中，该方法包括在衬底之上和晶体管之间形成由BPSG组成的层，在BPSG层中形成的开口中形成局部互连，在局部互连形成之后减小BPSG层的厚度，并形成 在BPSG层上方和局部互连之间的电介质层，其中介电层的介电常数大于约6.0。

公开(公告)号：US07153731B2

公开(公告)日：2006-12-26

申请号：US10236662

申请日：2002-09-05

申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。 源极/漏极区域形成在沟道区域的相对侧上。 绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。 形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。 半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。 半导体通道材料形成在空隙内。 相邻的源极/漏极区域横向靠近通道材料提供。 在通道材料上形成一个栅极。 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。

公开(公告)号：US07112482B2

公开(公告)日：2006-09-26

申请号：US10901538

申请日：2004-07-28

申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

IPC分类号： H01L21/8238

CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

公开(公告)号：US06987291B2

公开(公告)日：2006-01-17

申请号：US10236282

申请日：2002-09-05

申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

IPC分类号： H01L31/0328

CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

摘要： Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

摘要翻译： 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。

公开(公告)号：US20050266666A1

公开(公告)日：2005-12-01

申请号：US11191512

申请日：2005-07-28

申请人： Jigish Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd Abbott

发明人： Jigish Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd Abbott

IPC分类号： G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/412 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104

摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

摘要翻译： 根据本发明，在由多晶硅膜和金属，金属硅化物或金属氮化物的覆盖膜构成的多晶硅结构的全部或部分掺杂多晶硅层上形成超薄掩埋扩散阻挡层（UBDBL） 。 更具体地，根据本发明的一个实施例，提供了一种存储单元，其包括半导体衬底，P阱，N阱，N型有源区，P型有源区，隔离区，多晶硅栅电极 结构和扩散阻挡层。 P阱形成在半导体衬底中。 N阱形成在与P阱相邻的半导体衬底中。 N型有源区定义在P阱中，P型有源区定义在N阱中。 隔离区被配置为将N型有源区与P型有源区隔离。 多晶硅栅电极结构由多晶硅膜和上覆金属，金属硅化物或金属氮化物膜构成。 多晶硅膜包括由N型有源区形成的N +多晶硅层和由P型有源区形成的P +多晶硅层。 多晶硅膜与金属，金属硅化物或金属氮化物膜之间的多晶硅膜的大部分上的多硅化物栅电极结构中形成扩散阻挡层。