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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20180261607A1

    公开(公告)日：2018-09-13

    申请号：US15975761

    申请日：2018-05-09

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L27/11 ,  H01L29/49 ,  H01L29/78 ,  G11C11/412 ,  G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US09985038B2

    公开(公告)日：2018-05-29

    申请号：US15448585

    申请日：2017-03-02

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/417 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US09646678B2

    公开(公告)日：2017-05-09

    申请号：US15216327

    申请日：2016-07-21

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: G11C11/412 ,  H01L27/11 ,  G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US09449678B2

    公开(公告)日：2016-09-20

    申请号：US14752514

    申请日：2015-06-26

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L29/76 ,  H01L27/11 ,  G11C11/412 ,  G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

    Abstract translation: 构成SRAM单元的逆变器的P型阱区域被细分成两部分，它们设置在N型阱区域NW1的相对侧上，并且形成为使得形成晶体管的扩散层具有 没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

    Butted contact shape to improve SRAM leakage current
    5.
    发明授权
    Butted contact shape to improve SRAM leakage current 有权
    对接接触形状，提高SRAM漏电流

    公开(公告)号：US09337205B2

    公开(公告)日：2016-05-10

    申请号：US14662326

    申请日：2015-03-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzyh-Cheang Lee

    IPC: H01L27/11 ,  H01L21/768 ,  H01L23/485

    CPC classification number: H01L27/1104 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/00 ,  H01L2924/0002 ,  Y10S257/902 ,  Y10S257/903 ,  Y10S257/904

    Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.

    Abstract translation: 本公开涉及SRAM存储单元。 SRAM存储单元具有半导体衬底，其具有有源区和位于有源区上方的栅极区。 对接触点从有效区域上方的位置延伸到栅极区域上方的位置。 对接触点包含具有不同宽度的多个不同区域（即对接触点的较小尺寸），使得横跨有源区域和栅极区域的区域的宽度小于与有源区域或栅极区域接触的区域 。 通过使跨越有源区域和栅极区域的区域的宽度小于与有源区域或栅极接触的区域，在栅极区域与有源区域的接合处蚀刻速率降低，从而防止蚀刻 栅极材料和漏电流。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140357047A1

    公开(公告)日：2014-12-04

    申请号：US14458976

    申请日：2014-08-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Jun KAWAHARA ,  Naoya INOUE ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

    IPC: H01L49/02

    CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

    Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

    Abstract translation: 半导体器件包括：第一绝缘层（层间绝缘层），设置在第一绝缘层（层间绝缘层）上的电阻元件，至少其表面层为TaSiN层;以及层间绝缘层， 第一绝缘层（层间绝缘层）和电阻元件。 在层间绝缘层中设置多个具有与TaSiN层结合的端子的通孔塞。

    Semiconductor integrated circuit device and process for manufacturing the same
    9.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US08093681B2

    公开(公告)日：2012-01-10

    申请号：US13044260

    申请日：2011-03-09

    Applicant: Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    Inventor： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    IPC: H01L29/00 ,  H01L21/8234

    CPC classification number: H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

    Abstract translation: 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。 此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。 此外，通过使用诸如硅化的电阻降低装置来形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

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