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公开(公告)号：US07154978B2
公开(公告)日：2006-12-26
申请号：US10000914
申请日：2001-11-02
IPC分类号： H03D3/24
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
摘要翻译： 在几个实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个辅助延迟元件（162 ... 164,270,310）。 在一个实施例中，主延迟线（24）用于粗略地选择频率输出，而使用无源或有源的辅助延迟元件（162 ... 164,270,310）来增加初级 延迟线（24）。 在被动实施例中，通过从主延迟线（24）的输出抽头中选择分量作为被动次级延迟元件（310）的驱动信号来提供粗调和选择输出，可以进行粗略和精细的频率选择 从第二延迟元件（310）提供精细选择。
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公开(公告)号：US06891420B2
公开(公告)日：2005-05-10
申请号：US10036558
申请日：2001-12-21
CPC分类号： H03L7/22 , H03L7/0812 , H03L7/16
摘要： A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).
摘要翻译： 数字频率合成器包括一个或多个参考时钟（104,1316,1502A，1504A，1506A），其可选地通过一个或多个脉冲宽度减法器（106）耦合到一个或多个主延迟线（108,702,1502B ，1504B，1506B），其包括多个输出抽头（108B-108I，702B-702E）。 在参考时钟（104）的至少某些时段期间，多个输出抽头耦合到公共输出（130,1312,1508），从而产生具有超过一个或多个频率的频率的频率的输出信号 参考时钟。 耦合优选地由通过选通脉冲切换的传输门（114,128,720-724,1420-1434）完成，门脉冲经由选通信号延迟线（134-146,704）从解码器（148,150,1418）接收 -718,1404-1416）。
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公开(公告)号：US06353649B1
公开(公告)日：2002-03-05
申请号：US09584980
申请日：2000-06-02
申请人： David E. Bockleman , Jui-Kuo Juan
发明人： David E. Bockleman , Jui-Kuo Juan
IPC分类号： H03D324
CPC分类号： G06F7/68 , G06F1/025 , H03L7/0812 , H03L7/16
摘要： A direct digital synthesizer (200) includes a first accumulator (202) that acts as the frequency accumulator in order to generate the desired average frequency. A second accumulator (204) acts to generate a phase correction at each overflow, with the input into the phase correction accumulator (204) being a function of the input frequency. The clock signal of the phase correction accumulator (204) is the overflow signal (208) of the frequency accumulator (202). With this configuration, the frequency accumulator (202) generates the timing, and the phase correction accumulator (204) generates the interpolation value. The use of the two accumulators (202, 204) as described, eliminates the need to use a multiplier in the design which is a high current consumption device.
摘要翻译： 直接数字合成器（200）包括作为频率累加器的第一累加器（202），以便产生期望的平均频率。 第二累加器（204）用于在每个溢出时产生相位校正，其中相位校正累加器（204）的输入是输入频率的函数。 相位校正累加器（204）的时钟信号是频率累加器（202）的溢出信号（208）。 利用该配置，频率累加器（202）产生定时，相位校正累加器（204）产生插补值。 如上所述使用两个累加器（202,204），消除了在设计中使用乘法器的需要，该乘法器是高电流消耗装置。
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