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公开(公告)号：US07154978B2
公开(公告)日：2006-12-26
申请号：US10000914
申请日：2001-11-02
IPC分类号： H03D3/24
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
摘要翻译： 在几个实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个辅助延迟元件（162 ... 164,270,310）。 在一个实施例中，主延迟线（24）用于粗略地选择频率输出，而使用无源或有源的辅助延迟元件（162 ... 164,270,310）来增加初级 延迟线（24）。 在被动实施例中，通过从主延迟线（24）的输出抽头中选择分量作为被动次级延迟元件（310）的驱动信号来提供粗调和选择输出，可以进行粗略和精细的频率选择 从第二延迟元件（310）提供精细选择。
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公开(公告)号：US06891420B2
公开(公告)日：2005-05-10
申请号：US10036558
申请日：2001-12-21
CPC分类号： H03L7/22 , H03L7/0812 , H03L7/16
摘要： A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).
摘要翻译： 数字频率合成器包括一个或多个参考时钟（104,1316,1502A，1504A，1506A），其可选地通过一个或多个脉冲宽度减法器（106）耦合到一个或多个主延迟线（108,702,1502B ，1504B，1506B），其包括多个输出抽头（108B-108I，702B-702E）。 在参考时钟（104）的至少某些时段期间，多个输出抽头耦合到公共输出（130,1312,1508），从而产生具有超过一个或多个频率的频率的频率的输出信号 参考时钟。 耦合优选地由通过选通脉冲切换的传输门（114,128,720-724,1420-1434）完成，门脉冲经由选通信号延迟线（134-146,704）从解码器（148,150,1418）接收 -718,1404-1416）。
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3.发明授权公开(公告)号：US06539344B1
公开(公告)日：2003-03-25
申请号：US09553814
申请日：2000-04-21
IPC分类号： G06F760
CPC分类号： G06F17/5036
摘要： A parameter extraction technique for an electrical structure is based on a definition of network parameters that isolates pure mode responses of the electrical structure, and that makes mode conversion responses of the electrical structure negligible. A set of network parameters is obtained that represents pure mode responses for the electrical structure (410). These network parameters are processed to obtain model parameters that characterize each pure mode response (422, 424, 426, 428, 432, 434, 436, 438). Preferably, the mode specific parameters to combined to obtain mode independent parameters, such as coupling factor, propagation constant, and characteristic impedance values (440, 450).
摘要翻译： 用于电气结构的参数提取技术基于隔离电气结构的纯模式响应的网络参数的定义，并且使得电气结构的模式转换响应可忽略不计。 获得代表电结构（410）的纯模式响应的一组网络参数。 处理这些网络参数以获得表征每个纯模式响应（422,424,426,428,432,434,436,438）的模型参数。 优选地，组合的模式特定参数以获得模式无关参数，例如耦合因子，传播常数和特征阻抗值（440,450）。
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4.发明授权Interconnection structure for crosstalk reduction to improve off-chip selectivity 失效用于串扰降低的互连结构，以提高片外选择性
公开(公告)号：US5376902A
公开(公告)日：1994-12-27
申请号：US115291
申请日：1993-08-31
CPC分类号： H04B3/32 , H01L23/66 , H01L2224/05554 , H01L2224/48137 , H01L2224/49096 , H01L2224/49171 , H01L2224/49175 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/01055 , H01L2924/01057 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111
摘要： To reduce crosstalk in reentrant off-chip RF selectivity, differential circuits (402, 415), transmission lines (423, 424), and off-chip filters (422) are used in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit (402) and a receiving circuit (415). Two differential transmission lines (423, 424), each with constant characteristic impedance, and each with balanced capacitance to ground, both being closely spaced for some distance, couple the circuits (402, 415) to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines (423, 424). A second substrate (408) having a reentrant RF path (406) with the first substrate (409) contains an RF function such as a filter or a delay line.
摘要翻译： 为了减少重入片外RF选择性中的串扰，差分电路（402,415），传输线（423,424）和片外滤波器（422）被用于平衡与所有 微分元素 该结构包括具有差分发生电路（402）和接收电路（415）的衬底（409）。 两个差分传输线（423,424）每个具有恒定的特性阻抗，并且每个具有平衡电容对地，两者彼此紧密间隔一定距离，将电路（402,415）耦合到紧密间隔的端接焊盘（403）。 地平面（412）在两条传输线（423,424）下共享。 具有与第一衬底（409）的可重入RF路径（406）的第二衬底（408）包含诸如滤波器或延迟线的RF功能。
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公开(公告)号：US5379008A
公开(公告)日：1995-01-03
申请号：US25458
申请日：1993-03-03
CPC分类号： H03H7/06
摘要： An electronic circuit (300) includes first (302) and second (304) variable impedance devices coupled together. The first (302) and second (304) variable impedance devices are designed such that each exhibits a transfer function which is substantially inverse with respect to the other about the operating point of the electronic circuit. This provides for an electronic circuit which exhibits very low distortion characteristics. Circuits such as tunable filters, voltage-controlled oscillators (VCOs), receivers, etc. will benefit from using an electronic circuit (300) which exhibits such low distortion characteristics.
摘要翻译： 电子电路（300）包括耦合在一起的第一（302）和第二（304）可变阻抗器件。 第一（302）和第二（304）可变阻抗装置被设计成使得每个展现出相对于另一个绕电子电路的工作点基本上相反的传递函数。 这提供了具有非常低失真特性的电子电路。 诸如可调谐滤波器，压控振荡器（VCO），接收器等的电路将受益于使用具有这种低失真特性的电子电路（300）。
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公开(公告)号：US06198348B1
公开(公告)日：2001-03-06
申请号：US09346032
申请日：1999-07-01
IPC分类号： H03F345
CPC分类号： H03F1/48 , H03F3/4508 , H03F2200/36
摘要： A differential circuit (200) provides for reverse isolation between input and output ports (202, 204). The differential circuit has amplification circuitry that includes active transistors (221, 222) and reverse isolation circuitry that employ transistors (223,224) having similar manufacturing and processing characteristics to couple the input and output ports (202, 204).
摘要翻译： 差分电路（200）提供输入和输出端口（202,204）之间的反向隔离。 差分电路具有放大电路，其包括有源晶体管（221,222）和反向隔离电路，其采用具有相似制造和处理特性的晶体管（223,224）来耦合输入和输出端口（202,204）。
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7.发明授权Method and apparatus for reducing even order distortion in differential circuits 有权降低差分电路中偶数阶失真的方法和装置
公开(公告)号：US6118322A
公开(公告)日：2000-09-12
申请号：US185263
申请日：1998-11-03
摘要： An apparatus (100) includes a differential processing circuit (135) responsive to an input signal with first and second signal components, and a signal imbalance suppressor (130) that preprocesses the input signal, prior to input to the differential processing circuit, to remove amplitude and/or phase imbalances that exist between the first and second signal components, in order to reduce even order distortion generation within the differential processing circuit.
摘要翻译： 一种设备（100）包括响应于具有第一和第二信号分量的输入信号的差分处理电路（135），以及在输入到差分处理电路之前预处理输入信号的信号不平衡抑制器（130）以去除 存在于第一和第二信号分量之间的幅度和/或相位不平衡，以便减少差分处理电路内的偶数阶失真产生。
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8.发明授权Apparatus and method for generating accurate quadrature over a frequency range 有权用于在频率范围内产生精确正交的装置和方法公开(公告)号：US06222405B1
公开(公告)日：2001-04-24
申请号：US09507722
申请日：2000-02-22
IPC分类号： H03H1116
CPC分类号： H03H11/16
摘要： The invention produces an accurate quadrature relationship for a range of frequencies using passive components in the primary quadrature splitting circuits. A reference oscillator (202) generates a reference signal which is fed to a conventional passive quadrature splitter circuit (204). However, since the reference circuit provides signals over a range of frequencies, the output signals of the passive quadrature splitter may not have an accurate quadrature relationship. The output signals of the passive quadrature splitter are then equalized in magnitude, and the sum and difference of the signals are produced, which will be in an accurate quadrature relationship.
摘要翻译： 本发明使用主要正交分离电路中的无源部件在一定频率范围内产生精确的正交关系。 参考振荡器（202）产生馈送到常规无源正交分离器电路（204）的参考信号。 然而，由于参考电路在一定范围的频率上提供信号，所以无源正交分离器的输出信号可能不具有精确的正交关系。 然后，无源正交分波器的输出信号在幅度上相等，并且产生信号的和和差，这将在精确的正交关系中。
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公开(公告)号：US5615096A
公开(公告)日：1997-03-25
申请号：US254733
申请日：1994-06-06
IPC分类号： H01L23/522 , H02M3/07 , H01L17/00
CPC分类号： H02M3/07 , H01L23/5222 , H01L2924/0002 , H01L2924/3011
摘要： A power supply (200) includes a VVC (222) which provides for the efficient conversion of voltages with minimum ripple. The doping of the VVC (222) is altered such that most of the energy is delivered to a load (224) at a substantially constant voltage. The VVC (222) is fabricated using such materials as Zirconium Titanate. The VVC (222) has a high capacitance to volume ratio and therefore results in a significant reduction in the overall size of the power supply (200).
摘要翻译： 电源（200）包括VVC（222），其提供具有最小纹波的电压的有效转换。 VVC（222）的掺杂被改变，使得大部分能量以基本恒定的电压被传送到负载（224）。 VVC（222）使用钛酸锆等材料制造。 VVC（222）具有高的电容与体积比，因此导致电源（200）的总体尺寸的显着降低。
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10.发明授权公开(公告)号：US07162000B2
公开(公告)日：2007-01-09
申请号：US10050233
申请日：2002-01-16
CPC分类号： H03L7/0812 , H03K7/04 , H03K2005/00019 , H03L7/16 , H04L27/0008
摘要： A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.
摘要翻译： 一种产生多个输出的延迟锁定环路（200）。 单个延迟线（24）在多个分接选择电路（256A，265B，265C）之间共享。 可以在多个输出之间引入固定相移（412）。 调制信号可用于抽头选择处理以产生数字幅度，频率和/或相位调制。
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