公开(公告)号：US20240251561A1

公开(公告)日：2024-07-25

申请号：US18440623

申请日：2024-02-13

Applicant: Kioxia Corporation

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H10B43/35 ,  H01L21/8234 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/35 ,  H01L21/823437 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20230088310A1

公开(公告)日：2023-03-23

申请号：US17991694

申请日：2022-11-21

Applicant: KIOXIA CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.