公开(公告)号：US20240221799A1

公开(公告)日：2024-07-04

申请号：US18609522

申请日：2024-03-19

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C5/02 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C5/025 ,  G11C7/222

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20230290390A1

公开(公告)日：2023-09-14

申请号：US18316277

申请日：2023-05-12

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

CPC classification number: G11C7/1063 ,  G11C7/222 ,  G11C5/025

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20220351760A1

公开(公告)日：2022-11-03

申请号：US17864515

申请日：2022-07-14

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.