公开(公告)号：US20240321348A1

公开(公告)日：2024-09-26

申请号：US18675257

申请日：2024-05-28

Applicant: KIOXIA CORPORATION

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC: G11C11/56 ,  G06F12/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G06F12/0246

Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20220351760A1

公开(公告)日：2022-11-03

申请号：US17864515

申请日：2022-07-14

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20220284935A1

公开(公告)日：2022-09-08

申请号：US17749364

申请日：2022-05-20

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA

IPC: G11C7/22 ,  G11C7/10

Abstract: A semiconductor memory device according to an embodiment includes a first storage circuit. The first storage circuit is configured to store a first unique number uniquely assigned, and a first chip address having a bit number smaller than that of the first unique number and used to identify the semiconductor memory device from other semiconductor memory devices.

公开(公告)号：US20250095748A1

公开(公告)日：2025-03-20

申请号：US18967232

申请日：2024-12-03

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.

公开(公告)号：US20240111671A1

公开(公告)日：2024-04-04

申请号：US18267975

申请日：2020-12-28

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Masaki FUJIU

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A memory system according to an embodiment includes: a first chip including a first plane and a first input/output circuit; and a controller which is capable of issuing a command for controlling the first chip. The first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit which is capable of storing first read data read from the first memory cell array. The first input/output circuit includes a first FIFO circuit which is capable of fetching the first read data from the first latch circuit. The controller is capable of transmitting to the first chip a first command for ordering fetching of the first read data from the first latch circuit to the first FIFO circuit during a period in which a read operation is executed on the first plane.

公开(公告)号：US20230282257A1

公开(公告)日：2023-09-07

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa KUROSAWA ,  Akio SUGAHARA ,  Mitsuhiro ABE ,  Hisashi FUJIKAWA ,  Yuji NAGAI ,  Zhao LU

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/20 ,  G11C7/1069

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

公开(公告)号：US20230162788A1

公开(公告)日：2023-05-25

申请号：US18159123

申请日：2023-01-25

Applicant: KIOXIA CORPORATION

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G06F12/0246

Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20240347087A1

公开(公告)日：2024-10-17

申请号：US18754823

申请日：2024-06-26

Applicant: KIOXIA CORPORATION

Inventor： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20230317177A1

公开(公告)日：2023-10-05

申请号：US18205915

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Takaya HANDA ,  Ryosuke ISOMURA ,  Kazuto UEHARA ,  Junichi SATO ,  Norichika ASAOKA ,  Masashi YAMAOKA ,  Bushnaq SANAD ,  Yuzuru SHIBAZAKI ,  Noriyasu KUMAZAKI ,  Yuri TERADA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US20230297239A1

公开(公告)日：2023-09-21

申请号：US17898370

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Kenta SHIBASAKI ,  Yoshihiko SHINDO ,  Yasuhiro HIRASHIMA ,  Akio SUGAHARA ,  Shigeki NAGASAKA ,  Dai NAKAMURA ,  Yousuke HAGIWARA

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0653

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.