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公开(公告)号:US20210255942A1
公开(公告)日:2021-08-19
申请号:US17166417
申请日:2021-02-03
Inventor: Myoungsoo JUNG , Miryeong KWON , Gyuyoung PARK , SangWon LEE
Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.
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2.
公开(公告)号:US20230418673A1
公开(公告)日:2023-12-28
申请号:US18166685
申请日:2023-02-09
Inventor: Myoungsoo JUNG , Junhyeok JANG , Miryeong KWON , Donghyun GOUK , Hanyeoreum BAE
CPC classification number: G06F9/5027 , G06F9/54 , G06F9/4881
Abstract: Provided is an apparatus for accelerating a graph neural network for efficient parallel processing of massive graph datasets, including a streaming multiprocess (SM) scheduler and a computation unit, wherein the SM scheduler obtains a subgraph and an embedding table per layer, determines a number of SMs to be allocated for processing embeddings of a destination-vertex based on a feature dimension and a maximum number of threads in each of the SMs, and allocates the determined number of SMs to each of all destination-vertices included in the subgraph, and the computation unit obtains, by each of the SMs, embeddings of a destination-vertex allocated to each SM, obtains, by each SM, embeddings of at least one or more neighbor-vertices of the destination-vertex using the subgraph, and performs, by each SM, a user-designated operation using the embeddings of the destination-vertex and the embeddings of the neighbor-vertices.
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3.
公开(公告)号:US20240264957A1
公开(公告)日:2024-08-08
申请号:US18425079
申请日:2024-01-29
Inventor: Myoungsoo JUNG , Donghyun GOUK , Miryeong KWON
CPC classification number: G06F13/1673 , G06F12/0246 , G06F13/4221
Abstract: A compute express link (CXL) computing system includes a host device including a CPU that supports CXL, and a CXL storage connected to a CXL root port of the CPU based on the CXL interconnect and including a flash memory-based memory module.
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公开(公告)号:US20230221876A1
公开(公告)日:2023-07-13
申请号:US18151645
申请日:2023-01-09
Inventor: Myoungsoo JUNG , Miryeong KWON , Donghyun Gouk
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/061 , G06F3/0679
Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.
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