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公开(公告)号：US20230221876A1
公开(公告)日：2023-07-13
申请号：US18151645
申请日：2023-01-09
Inventor： Myoungsoo JUNG , Miryeong KWON , Donghyun Gouk
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/061 , G06F3/0679
Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.
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公开(公告)号：US20230007080A1
公开(公告)日：2023-01-05
申请号：US17561777
申请日：2021-12-24
Inventor： Myoungsoo Jung , Donghyun Gouk , Miryeong Kwon
IPC: H04L67/1097 , H04L69/08 , H04L67/60 , H04L67/568
Abstract: A first IP address is set to the host, and a second IP address is set to the storage card. A storage card includes a storage device and a processor for executing firmware. The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card. The firmware parses the NVMe request to perform the ISP-related request.
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公开(公告)号：US12248814B2
公开(公告)日：2025-03-11
申请号：US18453702
申请日：2023-08-22
Inventor： Myoungsoo Jung , Seungkwan Kang , Donghyun Gouk , Miryeong Kwon , Hyunkyu Choi , Junhyeok Jang
Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.
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Patent Agency Ranking
公开(公告)号：US20250036572A1
公开(公告)日：2025-01-30
申请号：US18511301
申请日：2023-11-16
Inventor： Shinhyun CHOI , Myoungsoo Jung , Hakcheon Jeong , See-On Park , Donghyun Gouk , Seonghyeon Jang
IPC: G06F12/12 , G06F12/0864
Abstract: A method and electronic circuit for memory replacement are provided. The method for memory replacement includes generating an input signal in response to an event for a memory, providing the input signal to a time-varying circuit including a plurality of time-varying devices, generating an output signal by reading a value stored in at least one time-varying device among the plurality of time-varying devices, and determining a storage space for replacement, based on the output signal.
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公开(公告)号：US12169636B2
公开(公告)日：2024-12-17
申请号：US18151645
申请日：2023-01-09
Inventor： Myoungsoo Jung , Miryeong Kwon , Donghyun Gouk
IPC: G06F3/06
Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.
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公开(公告)号：US20240303122A1
公开(公告)日：2024-09-12
申请号：US18453702
申请日：2023-08-22
Inventor： Myoungsoo JUNG , Seungkwan Kang , Donghyun Gouk , Miryeong Kwon , Hyunkyu CHOI , Junhyeok Jang
CPC classification number: G06F9/5027 , G06F7/36
Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.
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公开(公告)号：US20240281645A1
公开(公告)日：2024-08-22
申请号：US18450497
申请日：2023-08-16
Inventor： Myoungsoo JUNG , Seungkwan Kang , Donghyun Gouk , Miryeong Kwon , Hyunkyu Choi , Junhyeok Jang
IPC: G06N3/0495
CPC classification number: G06N3/0495
Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a conversion unit configured to convert an original graph in a coordinate list (COO) format into a graph in a compressed sparse row (CSR) format, a sub-graph generation unit configured to generate a sub-graph with a reduced degree of the graph in the CSR format, and an embedding table generation unit configured to generate an embedding table corresponding to the sub-graph.
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公开(公告)号：US11689621B2
公开(公告)日：2023-06-27
申请号：US17561777
申请日：2021-12-24
Inventor： Myoungsoo Jung , Donghyun Gouk , Miryeong Kwon
IPC: H04L67/1097 , H04L69/08 , H04L67/60 , H04L67/568
CPC classification number: H04L67/1097 , H04L67/568 , H04L67/60 , H04L69/08
Abstract: A first IP address is set to the host, and a second IP address is set to the storage card. A storage card includes a storage device and a processor for executing firmware. The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card. The firmware parses the NVMe request to perform the ISP-related request.
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