公开(公告)号：US07046298B2

公开(公告)日：2006-05-16

申请号：US10400930

申请日：2003-03-28

申请人： Keiichi Kuzumoto ,  Toshihiro Matsumura ,  Akihiro Suzuki ,  Atsuhisa Kageyama

发明人： Keiichi Kuzumoto ,  Toshihiro Matsumura ,  Akihiro Suzuki ,  Atsuhisa Kageyama

IPC分类号： H04N7/08 ,  H04N7/87 ,  H04N11/00 ,  H04N7/00

CPC分类号： H04L7/0331 ,  H04L7/046 ,  H04N7/035 ,  H04N7/0352 ,  H04N7/0355 ,  H04N7/088

摘要： This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.

摘要翻译： 本发明提供一种数据信号提取装置，即使发生相移等，也能够从串行发送的数据信号中精确地提取数据。 根据该装置，相移量计算电路13计算相移量S13，然后校正量计算电路14基于相移量S13计算校正量S14，提取间隔校正电路10 基于校正量校正提取间隔值S 9，并且提取脉冲产生电路11基于校正的提取间隔值S10生成提取脉冲S 11，从而从二进制信号S 8中提取数据 提取脉冲的基础。

公开(公告)号：US06909467B2

公开(公告)日：2005-06-21

申请号：US09845027

申请日：2001-05-01

申请人： Keiichi Kuzumoto ,  Toshihiro Matsumura

发明人： Keiichi Kuzumoto ,  Toshihiro Matsumura

IPC分类号： H04H20/00 ,  H04H20/28 ,  H04H40/18 ,  H04H60/13 ,  H04N5/445 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N11/00 ,  H04N7/00

CPC分类号： H04H40/18 ,  H04H20/28 ,  H04H60/13 ,  H04N7/035

摘要： A broadcast text data sampling apparatus comprises an A/D converter for sampling a broadcast text signal supplied from the outside, with a sampling clock of a predetermined frequency, to convert the text signal into digital data; a binarization circuit for converting the digital data into a binary signal; a sampling pulse generation circuit for detecting the cycle of clock run-in of the broadcast text signal from the binary signal, obtaining a text data sampling interval value on the basis of the clock run-in cycle, sequentially calculating the positions of data in the binary signal, which data are positioned at intervals close to the sampling interval value, starting from a predetermined sampling start position, and generating a sampling pulse that designates the calculated data positions as data sampling positions; and a sampling circuit for sampling the text data from the binary signal on the basis of the sampling pulse. Therefore, this data sampling apparatus is able to perform sampling of text data from plural types of text broadcastings having different transmission clock frequencies.

摘要翻译： 广播文本数据采样装置包括：A / D转换器，用于对从外部提供的广播文本信号采样预定频率的采样时钟，将文本信号转换成数字数据; 用于将数字数据转换为二进制信号的二值化电路; 采样脉冲发生电路，用于检测来自二进制信号的广播文本信号的时钟周期的周期，基于时钟输入周期获得文本数据采样间隔值，依次计算数据的位置 二进制信号，从预定的采样开始位置开始，数据以接近采样间隔值的间隔定位，并产生指定计算的数据位置作为数据采样位置的采样脉冲; 以及采样电路，用于根据采样脉冲对来自二进制信号的文本数据进行采样。 因此，该数据采样装置能够对具有不同传输时钟频率的多种类型的文本广播进行文本数据的采样。

公开(公告)号：US07321637B2

公开(公告)日：2008-01-22

申请号：US11041215

申请日：2005-01-25

申请人： Keiichi Kuzumoto

发明人： Keiichi Kuzumoto

IPC分类号： H04L25/06 ,  H04L25/10

CPC分类号： H04N7/0355

摘要： A data slice control device comprises a monotone increase detection circuit for detecting a monotone increase point of a data signal, a monotone decrease detection circuit for detecting a monotone decrease point of the data signal, a counter for calculating a monotone increase interval value from the monotone increase point to a next monotone increase point, a data holding circuit for calculating a monotone increase monotone decrease interval value from the monotone increase point to the monotone decrease point, a CRI period determination circuit for determining whether the data signal is within a CRI period or not on the basis of the monotone increase interval value and the monotone increase monotone decrease interval value, and a slice level calculation circuit for calculating a slice level from a maximum value and a minimum value of amplitude values of the data signal only when the data signal is within the CRI period.

摘要翻译： 数据切片控制装置包括用于检测数据信号的单调增加点的单调增加检测电路，用于检测数据信号的单调降低点的单调递减检测电路，用于从单调计算单调增加间隔值的计数器 增加点到下一个单调增加点，用于计算从单调增加点到单调减少点的单调递增单调递减间隔值的数据保持电路，用于确定数据信号是否在CRI周期内的CRI周期确定电路， 不是基于单调增加间隔值和单调增加单调减小间隔值的基础上的限幅电平计算电路，以及仅在数据信号时仅从数据信号的幅度值的最大值和最小值计算限幅电平的限幅电平计算电路 在CRI期间内。

公开(公告)号：US5796437A

公开(公告)日：1998-08-18

申请号：US761431

申请日：1996-12-06

申请人： Tsutomu Muraji ,  Keiichi Kuzumoto ,  Satoshi Hirotsune ,  Mitsuru Kotaka

发明人： Tsutomu Muraji ,  Keiichi Kuzumoto ,  Satoshi Hirotsune ,  Mitsuru Kotaka

IPC分类号： H04N5/14 ,  H04N5/44 ,  H04N7/26 ,  H04N7/36 ,  H04N7/46 ,  H04N7/01 ,  H04N11/20

CPC分类号： H04N19/40 ,  H04N19/51 ,  H04N19/587 ,  H04N5/145 ,  H04N7/012

摘要： A progressive scanning conversion apparatus for converting an interlaced scan video signal into a progressive scan video signal by performing interpolation based on original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a current field, original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a previous field which is immediately prior to the current field, and original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a next field which is immediately following the current field. The apparatus includes a motion vector detector for detecting a motion vector between two of the current field, the previous field, and the next field; a motion estimation circuit for estimating a pixel value in the current field, from one of a pixel in the previous field and a pixel in the next field using the motion vector detected by the vector detection means; and an interpolated pixel generator for generating an interpolated pixel used for conversion by multiplying the pixel value obtained by the motion estimation means and the corresponding pixel value in the current field by a weighting factor and summating the multiplication results.

公开(公告)号：US20060268170A1

公开(公告)日：2006-11-30

申请号：US11500464

申请日：2006-08-08

申请人： Akihiro Suzuki ,  Keiichi Kuzumoto

发明人： Akihiro Suzuki ,  Keiichi Kuzumoto

IPC分类号： H04N11/00 ,  H03M1/12

CPC分类号： H04N7/035 ,  H04N7/0355 ,  H04N7/0357 ,  H04N7/0882

摘要： A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

摘要翻译： 数据限幅器300包括限幅电平计算单元310，其基于信号的幅度来确定检测到的数字视频信号是否为CRI信号，并且设置参考限幅电平和通过提供 通过仅使用CRI信号在参考限幅电平中的偏移; 数据切片单元160，其使用切片级对数字视频信号S140进行二值化; 将二值化的串行数据转换为并行数据的解码电路170; 以及数据选择单元320，其从解码数据中选择不包含错误的数据，并通过视频信号输出端子190输出所选择的数据。 因此，即使当视频信号失真时，该数据限幅器也可以设置合适的限幅电平数据来二值化视频信号，从而抑制解码错误的发生率。

公开(公告)号：US07098960B2

公开(公告)日：2006-08-29

申请号：US10611433

申请日：2003-07-02

申请人： Akihiro Suzuki ,  Keiichi Kuzumoto

发明人： Akihiro Suzuki ,  Keiichi Kuzumoto

IPC分类号： H04N7/00

CPC分类号： H04N7/035 ,  H04N7/0355 ,  H04N7/0357 ,  H04N7/0882

摘要： A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

公开(公告)号：US20050162298A1

公开(公告)日：2005-07-28

申请号：US11041215

申请日：2005-01-25

申请人： Keiichi Kuzumoto

发明人： Keiichi Kuzumoto

IPC分类号： H04N7/025 ,  H03M1/12 ,  H04N7/03 ,  H04N7/035

CPC分类号： H04N7/0355

摘要： A data slice control device comprises a monotone increase detection circuit for detecting a monotone increase point of a data signal, a monotone decrease detection circuit for detecting a monotone decrease point of the data signal, a counter for calculating a monotone increase interval value from the monotone increase point to a next monotone increase point, a data holding circuit for calculating a monotone increase monotone decrease interval value from the monotone increase point to the monotone decrease point, a CRI period determination circuit for determining whether the data signal is within a CRI period or not on the basis of the monotone increase interval value and the monotone increase monotone decrease interval value, and a slice level calculation circuit for calculating a slice level from a maximum value and a minimum value of amplitude values of the data signal only when the data signal is within the CRI period.

摘要翻译： 数据切片控制装置包括用于检测数据信号的单调增加点的单调增加检测电路，用于检测数据信号的单调降低点的单调递减检测电路，用于从单调计算单调增加间隔值的计数器 增加点到下一个单调增加点，用于计算从单调增加点到单调减少点的单调递增单调递减间隔值的数据保持电路，用于确定数据信号是否在CRI周期内的CRI周期确定电路， 不是基于单调增加间隔值和单调增加单调减小间隔值的基础上的限幅电平计算电路，以及仅在数据信号时仅从数据信号的幅度值的最大值和最小值计算限幅电平的限幅电平计算电路 在CRI期间内。

公开(公告)号：US20100020243A1

公开(公告)日：2010-01-28

申请号：US12521968

申请日：2008-09-09

申请人： Katsuyuki Kitano ,  Keiichi Kuzumoto ,  Atsuhisa Kageyama

发明人： Katsuyuki Kitano ,  Keiichi Kuzumoto ,  Atsuhisa Kageyama

IPC分类号： H04N5/16

CPC分类号： H04N5/18 ,  G09G5/003 ,  H04N5/46 ,  H04N21/426 ,  H04N21/4436

摘要： In a video signal processor (10), a video signal is given to a video input terminal (101) via a coupling capacitor (200). A clamp circuit (104) clamps the video signal input via the video input terminal (101). A format detector section (105) detects a format of the video signal. A controller section (107) changes power supply capability of the clamp circuit (104) according to a detection result of the format detector section (105).

摘要翻译： 在视频信号处理器（10）中，通过耦合电容器（200）向视频输入端子（101）提供视频信号。 钳位电路（104）经由视频输入端（101）钳位输入的视频信号。 格式检测器部分（105）检测视频信号的格式。 控制部（107）根据格式检测部（105）的检测结果来改变钳位电路（104）的供电能力。

公开(公告)号：US07599003B2

公开(公告)日：2009-10-06

申请号：US11500464

申请日：2006-08-08

申请人： Akihiro Suzuki ,  Keiichi Kuzumoto

发明人： Akihiro Suzuki ,  Keiichi Kuzumoto

IPC分类号： H04N7/00

CPC分类号： H04N7/035 ,  H04N7/0355 ,  H04N7/0357 ,  H04N7/0882

摘要： A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

摘要翻译： 数据限幅器300包括限幅电平计算单元310，其基于信号的幅度来确定检测到的数字视频信号是否为CRI信号，并且设置参考限幅电平和通过提供 通过仅使用CRI信号在参考限幅电平中的偏移; 数据切片单元160，其使用切片级对数字视频信号S140进行二值化; 将二值化的串行数据转换为并行数据的解码电路170; 以及数据选择单元320，其从解码数据中选择不包括错误的数据，并通过视频信号输出端子190输出所选择的数据。因此，即使视频信号失真，该数据限幅器也可以将适当的限幅电平数据设置为 二值化视频信号，从而抑制解码错误的发生率。

公开(公告)号：US20090237558A1

公开(公告)日：2009-09-24

申请号：US12307683

申请日：2008-05-14

申请人： Kazuya Miyashita ,  Keiichi Kuzumoto

发明人： Kazuya Miyashita ,  Keiichi Kuzumoto

IPC分类号： H04N7/00

CPC分类号： H04N7/035

摘要： A band-pass filter (131), which extracts a frequency component of a teletext reference signal from a digital input signal obtained by digitizing a composite signal, is provided in a frequency characteristic enhancement circuit (130). A determination circuit (145), which determines a state of the composite signal in accordance with maximum and minimum values of an output of the frequency characteristic enhancement circuit (130) during the period of the teletext reference signal and in accordance with maximum and minimum values of the output of the frequency characteristic enhancement circuit (130) during the period of time between a current horizontal synchronization interval and a next horizontal synchronization interval, is provided in a slicing circuit (140). A signal to be output to the slicing circuit (140) is generated by the frequency characteristic enhancement circuit (130) in accordance with either an output of the band-pass filter (131) or the digital input signal which is selected according to a determination result obtained by the determination circuit (145).

摘要翻译： 在频率特性增强电路（130）中提供了一种从通过数字化复合信号获得的数字输入信号中提取图文电视参考信号的频率分量的带通滤波器（131）。 一种确定电路（145），其根据图文电视参考信号期间的频率特性增强电路（130）的输出的最大值和最小值，并根据最大值和最小值确定复合信号的状态 在切片电路（140）中提供频率特性增强电路（130）在当前水平同步间隔和下一个水平同步间隔之间的时间段期间的输出。 根据频带特性增强电路（130）根据带通滤波器（131）的输出或根据确定的选择的数字输入信号产生要输出到限幅电路（140）的信号 由确定电路（145）获得的结果。