Abstract:
In an exemplary embodiment of the present disclosure, a thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode on a non-pixel area of a substrate includes a first insulating layer that insulates the gate electrode from the source electrode and the drain electrode, and a second insulating layer that covers the source electrode and the drain electrode. According to an exemplary embodiment of the present disclosure, the first insulating layer and the second insulating layer are configured so as not to be extended to a pixel area of the substrate in order to reduce possible oscillation of transmittance depending on a viewing angle which occurs when a specific light of a light source passes through the pixel area.
Abstract:
A liquid crystal display panel includes features to prevent damage to the liquid crystal alignment layer when a color filter substrate and a thin-film transistor array substrate are moved relative to each other. The liquid crystal display panel may include a column spacer on the color filter substrate under the black matrix and a bump pattern on the array substrate where the column spacer and the bump pattern are in contact with each other. The array substrate may otherwise include a planarization layer with a step portion and a protective layer on the planarization layer where the protective layer is in contact with the column spacer.
Abstract:
An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.
Abstract:
A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.
Abstract:
An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.
Abstract:
A display device according to an embodiment includes a lower substrate in which a display area and a non-display area are divided and an upper substrate which corresponds to the lower substrate and includes a black matrix BM. Further, the display device can include a bezel which is located on the non-display area and includes a GIP driver, a plurality of signal transmission lines, a connection line connecting the GIP driver and the plurality of signal transmission lines, and a seal area equipped with a sealant, in a direction being apart from one side of the display area, a plurality of bridge patterns which is located on the non-display area and electrically connects the GIP driver and the connection line, and the connection line and the plurality of signal transmission lines, respectively, and a plurality of shield patterns enclosing the plurality of bridge patterns. Also, the display device can include a plurality of shield patterns which minimize an area in which the sealant and the plurality of bridge patterns are in directly contact with each other.