公开(公告)号：US10600369B2

公开(公告)日：2020-03-24

申请号：US15835171

申请日：2017-12-07

Applicant: LG DISPLAY CO., LTD.

Inventor： Taehun Kim ,  Kitae Kwon ,  Kyujin Kim ,  Jiah Kim

IPC: G09G3/3291 ,  G09G3/3233 ,  G09G3/3258

Abstract: The disclosure relates to data driver and organic light emitting display device. The data driver includes: an input unit configured to receive an input data; a compensation data generator configured to generate a compensation data by applying a compensation value to the input data; a converter unit configured to convert the input data into an image data voltage and to convert the compensation data into a compensation data voltage; and an output unit configured to separately output the image data voltage and the compensation data voltage to a data line of the organic light emitting display.

公开(公告)号：US10180752B2

公开(公告)日：2019-01-15

申请号：US15605621

申请日：2017-05-25

Applicant: LG Display Co., Ltd.

Inventor： Jiah Kim ,  Byeongseong So

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/36 ,  G02F1/1333

Abstract: A display device and a gate driver circuit of the display device are disclosed. The display device includes a shift register that shifts a gate pulse in accordance with a shift clock and sequentially supplies the gate pulse to gate lines. At least one stage of the shift register includes a discharge blocking node connected to a source terminal of the second transistor, and a discharge blocking circuit configured to charge the discharge blocking node when the Q node is charged, and discharge the discharge blocking node when the Q node is discharged.

公开(公告)号：US20170032731A1

公开(公告)日：2017-02-02

申请号：US14983736

申请日：2015-12-30

Applicant: LG Display Co., Ltd.

Inventor： Dahye Shim ,  Joungmi Choi ,  Youngsung Cho ,  Jiah Kim

IPC: G09G3/20 ,  G06F1/26

CPC classification number: G09G3/2092 ,  G06F1/263 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/026 ,  G09G2330/027 ,  G09G2330/028

Abstract: A display device having a plurality of gate lines and a gate drive circuit is disclosed. The gate drive circuit includes a pull-up transistor configured to receive a first clock signal and to charge an output node to a voltage of the first clock signal based on a voltage of a Q node. The output node is connected to a corresponding one of the gate lines. The gate drive circuit also includes a switching circuit configured to charge the Q node based on a second clock signal. The switching circuit has an inverter circuit configured to control the voltage of the Q node based on the second clock signal.

Abstract translation: 公开了具有多条栅极线和栅极驱动电路的显示装置。 栅极驱动电路包括被配置为接收第一时钟信号并且基于Q节点的电压将输出节点充电到第一时钟信号的电压的上拉晶体管。 输出节点连接到相应的一条栅极线。 栅极驱动电路还包括被配置为基于第二时钟信号对Q节点充电的开关电路。 开关电路具有逆变器电路，被配置为基于第二时钟信号来控制Q节点的电压。

公开(公告)号：US10446070B2

公开(公告)日：2019-10-15

申请号：US14818761

申请日：2015-08-05

Applicant: LG Display Co., Ltd.

Inventor： Jiah Kim ,  Juyoung Lee ,  Byeongseong So ,  Seungjun Lee

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

Abstract: Provided are a display device, a scan driver, and a method of manufacturing the same. A scan driver includes: a level shifter configured to output a power and a signal, and a scan signal generating circuit configured to generate a scan signal based on the power and the signal supplied from the level shifter, the scan signal generating circuit including a buffer configured to transmit a clock signal to a stage of a shift register, the buffer including two inverters, one of the two inverters being included in a multi-buffer.

公开(公告)号：US10019929B2

公开(公告)日：2018-07-10

申请号：US14983736

申请日：2015-12-30

Applicant: LG Display Co., Ltd.

Inventor： Dahye Shim ,  Joungmi Choi ,  Youngsung Cho ,  Jiah Kim

IPC: G06F3/038 ,  G09G5/00 ,  G09G3/20 ,  G09G3/36 ,  G06F1/26

CPC classification number: G09G3/2092 ,  G06F1/263 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/026 ,  G09G2330/027 ,  G09G2330/028

Abstract: A display device having a plurality of gate lines and a gate drive circuit is disclosed. The gate drive circuit includes a pull-up transistor configured to receive a first clock signal and to charge an output node to a voltage of the first clock signal based on a voltage of a Q node. The output node is connected to a corresponding one of the gate lines. The gate drive circuit also includes a switching circuit configured to charge the Q node based on a second clock signal. The switching circuit has an inverter circuit configured to control the voltage of the Q node based on the second clock signal.