公开(公告)号：US11798497B2

公开(公告)日：2023-10-24

申请号：US17879052

申请日：2022-08-02

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun Lim ,  Nakwoo Kim ,  Donghyang Lee

IPC: G09G3/3291 ,  G09G3/3266

CPC classification number: G09G3/3291 ,  G09G3/3266 ,  G09G2310/0278 ,  G09G2310/08

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US11436983B2

公开(公告)日：2022-09-06

申请号：US17137084

申请日：2020-12-29

Applicant: LG Display Co., Ltd.

Inventor： Sanghyun Lim ,  Nakwoo Kim ,  Donghyang Lee

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US12154517B2

公开(公告)日：2024-11-26

申请号：US18368230

申请日：2023-09-14

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun Lim ,  Nakwoo Kim ,  Donghyang Lee

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US09853097B2

公开(公告)日：2017-12-26

申请号：US15299364

申请日：2016-10-20

Applicant: LG Display Co., Ltd.

Inventor： Nakwoo Kim ,  Jaeho Sim ,  Donghyun Yeo

IPC: H01L29/08 ,  H01L27/32

CPC classification number: H01L27/3276 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3225 ,  H01L27/3272

Abstract: An organic light emitting display in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting diode based on a voltage applied to a gate electrode, includes the gate electrode of the driving thin film transistor; a signal line adjacent to the gate electrode of the driving thin film transistor; and a first shielding electrode located above the gate electrode of the driving thin film transistor, with a first insulating layer therebetween, wherein the first shielding electrode extends further towards the signal line than the gate electrode of the driving thin film transistor.