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公开(公告)号:US08392657B2
公开(公告)日:2013-03-05
申请号:US12587670
申请日:2009-10-09
申请人: Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人: Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
CPC分类号: G06F12/0864
摘要: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译: 公开了一种装置,方法和系统。 在一个实施例中,该装置包括多个组的高速缓冲存储器。 高速缓冲存储器中的每个集合具有多个高速缓存行。 该装置还包括至少一个进程资源表。 进程资源表维护多个高速缓存行的高速缓存行占用数。 具体地说,每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。 此外,处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。
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公开(公告)号:US20110087843A1
公开(公告)日:2011-04-14
申请号:US12587670
申请日:2009-10-09
申请人: Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人: Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
CPC分类号: G06F12/0864
摘要: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译: 公开了一种装置,方法和系统。 在一个实施例中,该装置包括多个组的高速缓冲存储器。 高速缓冲存储器中的每个集合具有多个高速缓存行。 该装置还包括至少一个进程资源表。 进程资源表维护多个高速缓存行的高速缓存行占用数。 具体地说,每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。 此外,处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。
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公开(公告)号:US20110113200A1
公开(公告)日:2011-05-12
申请号:US12616066
申请日:2009-11-10
申请人: Jaideep Moses , Rameshkumar G. Illikkal , Donald K. Newell , Ravishankar Iyer , Kostantinos Alsopos , Li Zhao
发明人: Jaideep Moses , Rameshkumar G. Illikkal , Donald K. Newell , Ravishankar Iyer , Kostantinos Alsopos , Li Zhao
CPC分类号: G06F12/0888 , G06F11/3471 , G06F2201/885
摘要: Embodiments of an apparatus for controlling cache occupancy rates are presented. In one embodiment, an apparatus comprises a controller and monitor logic. The monitor logic determines a monitored occupancy rate associated with a first program class. The first controller regulates a first allocation probability corresponding to the first program class, based at least on the difference between a requested occupancy rate and the first monitored occupancy rate.
摘要翻译: 呈现用于控制高速缓存占用率的装置的实施例。 在一个实施例中,装置包括控制器和监视器逻辑。 监视器逻辑确定与第一程序类相关联的监视占用率。 第一控制器至少基于所请求的占用率和第一监视占用率之间的差异来调节与第一程序类相对应的第一分配概率。
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公开(公告)号:US08781234B2
公开(公告)日:2014-07-15
申请号:US12896077
申请日:2010-10-01
CPC分类号: G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
摘要翻译: 识别图像的方法和系统可以包括具有硬件模块的装置,该硬件模块具有对于图像中的多个向量的逻辑,基于图像矢量的偶数像素确定第一中间计算,并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。
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5.
公开(公告)号:US07490191B2
公开(公告)日:2009-02-10
申请号:US11525980
申请日:2006-09-22
IPC分类号: G06F12/10
CPC分类号: G06F12/1036 , G06F12/0284 , G06F12/109 , G06F2212/656
摘要: Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.
摘要翻译: 公开了在虚拟机环境中在客人之间共享信息的装置,方法和系统的实施例。 在一个实施例中,装置包括虚拟机控制逻辑,执行单元和存储器管理单元。 虚拟机控制逻辑是在主机及其客人之间传送设备的控制。 执行单元执行将来自虚拟地址空间中的虚拟存储器地址的信息复制到另一访客虚拟地址空间中的虚拟存储器地址的指令。 内存管理单元将虚拟内存地址转换为物理内存地址。
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公开(公告)号:US20120082387A1
公开(公告)日:2012-04-05
申请号:US12896077
申请日:2010-10-01
IPC分类号: G06K9/46
CPC分类号: G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
摘要翻译: 识别图像的方法和系统可以包括具有硬件模块的装置,该硬件模块具有对于图像中的多个向量的逻辑,基于图像矢量的偶数像素确定第一中间计算,并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。
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公开(公告)号:US20140314323A1
公开(公告)日:2014-10-23
申请号:US14320092
申请日:2014-06-30
CPC分类号: G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
摘要翻译: 识别图像的方法和系统可以包括具有硬件模块的装置,该硬件模块具有对于图像中的多个向量的逻辑,基于图像矢量的偶数像素确定第一中间计算,并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。
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公开(公告)号:US20080244221A1
公开(公告)日:2008-10-02
申请号:US11694322
申请日:2007-03-30
申请人: Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
发明人: Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
IPC分类号: G06F15/00
CPC分类号: G06F15/16
摘要: Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.
摘要翻译: 公开了将系统拓扑暴露给执行环境的装置,方法和系统的实施例。 在一个实施例中,装置包括在单个集成电路上的执行核心和资源以及拓扑逻辑。 拓扑逻辑是使用关于执行核心和资源之间的关系的信息来填充数据结构。
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公开(公告)号:US09626586B2
公开(公告)日:2017-04-18
申请号:US14320092
申请日:2014-06-30
CPC分类号: G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
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10.
公开(公告)号:US20080077765A1
公开(公告)日:2008-03-27
申请号:US11525980
申请日:2006-09-22
IPC分类号: G06F12/00
CPC分类号: G06F12/1036 , G06F12/0284 , G06F12/109 , G06F2212/656
摘要: Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.
摘要翻译: 公开了在虚拟机环境中在客人之间共享信息的装置,方法和系统的实施例。 在一个实施例中,装置包括虚拟机控制逻辑,执行单元和存储器管理单元。 虚拟机控制逻辑是在主机及其客人之间传送设备的控制。 执行单元执行将来自虚拟地址空间中的虚拟存储器地址的信息复制到另一访客的虚拟地址空间中的虚拟存储器地址的指令。 内存管理单元将虚拟内存地址转换为物理内存地址。
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