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1.
公开(公告)号:US07490191B2
公开(公告)日:2009-02-10
申请号:US11525980
申请日:2006-09-22
IPC分类号: G06F12/10
CPC分类号: G06F12/1036 , G06F12/0284 , G06F12/109 , G06F2212/656
摘要: Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.
摘要翻译: 公开了在虚拟机环境中在客人之间共享信息的装置,方法和系统的实施例。 在一个实施例中,装置包括虚拟机控制逻辑,执行单元和存储器管理单元。 虚拟机控制逻辑是在主机及其客人之间传送设备的控制。 执行单元执行将来自虚拟地址空间中的虚拟存储器地址的信息复制到另一访客虚拟地址空间中的虚拟存储器地址的指令。 内存管理单元将虚拟内存地址转换为物理内存地址。
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2.
公开(公告)号:US20080077765A1
公开(公告)日:2008-03-27
申请号:US11525980
申请日:2006-09-22
IPC分类号: G06F12/00
CPC分类号: G06F12/1036 , G06F12/0284 , G06F12/109 , G06F2212/656
摘要: Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.
摘要翻译: 公开了在虚拟机环境中在客人之间共享信息的装置,方法和系统的实施例。 在一个实施例中,装置包括虚拟机控制逻辑,执行单元和存储器管理单元。 虚拟机控制逻辑是在主机及其客人之间传送设备的控制。 执行单元执行将来自虚拟地址空间中的虚拟存储器地址的信息复制到另一访客的虚拟地址空间中的虚拟存储器地址的指令。 内存管理单元将虚拟内存地址转换为物理内存地址。
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公开(公告)号:US20080244221A1
公开(公告)日:2008-10-02
申请号:US11694322
申请日:2007-03-30
申请人: Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
发明人: Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
IPC分类号: G06F15/00
CPC分类号: G06F15/16
摘要: Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.
摘要翻译: 公开了将系统拓扑暴露给执行环境的装置,方法和系统的实施例。 在一个实施例中,装置包括在单个集成电路上的执行核心和资源以及拓扑逻辑。 拓扑逻辑是使用关于执行核心和资源之间的关系的信息来填充数据结构。
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公开(公告)号:US20160306415A1
公开(公告)日:2016-10-20
申请号:US15192134
申请日:2016-06-24
申请人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC分类号: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号:US20130262902A1
公开(公告)日:2013-10-03
申请号:US13992361
申请日:2011-09-06
申请人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC分类号: G06F1/32
CPC分类号: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括一种用于从加速器接收中断的方法,响应于该中断将恢复信号直接发送到小型核心,并向第一小型核心提供大型核心的执行状态的子集,以及 确定小型核心是否可以处理与该中断有关的请求,如果该确定是肯定的,则执行与该小核心中的该请求相对应的操作,否则将大的核心执行状态和恢复信号提供给该大核心 。 描述和要求保护其他实施例。
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公开(公告)号:US09360927B2
公开(公告)日:2016-06-07
申请号:US13992361
申请日:2011-09-06
申请人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC分类号: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括一种用于从加速器接收中断的方法,响应于该中断将恢复信号直接发送到小型核心,并向第一小型核心提供大型核心的执行状态的子集,以及 确定小型核心是否可以处理与该中断有关的请求,如果该确定是肯定的,则执行与该小核心中的该请求相对应的操作,否则将大的核心执行状态和恢复信号提供给该大核心 。 描述和要求保护其他实施例。
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公开(公告)号:US20140258685A1
公开(公告)日:2014-09-11
申请号:US13992856
申请日:2011-12-30
申请人: Srihari Makineni , Steven R. King , Alexander Redkin , Joshua B. Fryman , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov
发明人: Srihari Makineni , Steven R. King , Alexander Redkin , Joshua B. Fryman , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov
IPC分类号: G06F9/30
CPC分类号: G06F9/30145 , G06F1/3234 , G06F9/30181 , G06F9/30196 , G06F9/3891
摘要: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
摘要翻译: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此,在一些实施例中,可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理,使得包括部分核心的整体处理器可以完全向后兼容。
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公开(公告)号:US20140095799A1
公开(公告)日:2014-04-03
申请号:US13631894
申请日:2012-09-29
申请人: Zhen Fang , Shih-Lien Lu , Ravishankar Iyer , Srihari Makineni
发明人: Zhen Fang , Shih-Lien Lu , Ravishankar Iyer , Srihari Makineni
IPC分类号: G06F12/12
CPC分类号: G06F11/004 , G06F1/3225 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C5/141 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要: Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.
摘要翻译: 系统和方法可以提供确定存储器访问请求是否是容错的,以及如果存储器访问请求是容错的,则将存储器访问请求路由到可靠的存储器区域。 此外,如果存储器访问请求是容错的,则存储器访问请求可以被路由到不可靠的存储器区域。 在一个示例中,使用不可靠的存储区域使得能够降低包含可靠和不可靠的存储器区域的管芯的最小工作电压电平。
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公开(公告)号:US20080040555A1
公开(公告)日:2008-02-14
申请号:US11503777
申请日:2006-08-14
申请人: Ravishankar Iyer , Li Zhao , Srihari Makineni , Donald Newell
发明人: Ravishankar Iyer , Li Zhao , Srihari Makineni , Donald Newell
CPC分类号: G06F12/0811 , G06F12/0831
摘要: In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括一种用于在与第一级高速缓存耦合的第二级高速缓存中的数据非包含地维护第一级高速缓存中的数据的方法。 同时,可以与第二级高速缓存的目录部分一起保持与第一级高速缓存中的数据相关联的目录信息的至少一部分。 描述和要求保护其他实施例。
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公开(公告)号:US20060072563A1
公开(公告)日:2006-04-06
申请号:US10959488
申请日:2004-10-05
申请人: Greg Regnier , Vikram Saletore , Gary McAlpine , Ram Huggahalli , Ravishankar Iyer , Ramesh Illikkal , David Minturn , Donald Newell , Srihari Makineni
发明人: Greg Regnier , Vikram Saletore , Gary McAlpine , Ram Huggahalli , Ravishankar Iyer , Ramesh Illikkal , David Minturn , Donald Newell , Srihari Makineni
IPC分类号: H04L12/56
CPC分类号: H04L49/9094 , H04L49/90 , H04L49/9042 , H04L49/9063
摘要: In general, the disclosure describes a variety of techniques that can enhance packet processing operations.
摘要翻译: 通常,本公开描述了可以增强分组处理操作的各种技术。
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