公开(公告)号：US20080127192A1

公开(公告)日：2008-05-29

申请号：US11466903

申请日：2006-08-24

申请人： Louis B. Capps ,  Thomas J. Dewkett ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

发明人： Louis B. Capps ,  Thomas J. Dewkett ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

IPC分类号： G06F9/46

CPC分类号： G06F9/5044 ,  G06F1/3203 ,  G06F1/329 ,  Y02D10/24

摘要： A method, apparatus, and computer program product for using a multi-core integrated circuit having cores with differing performance characteristics. The cores are arranged into high and low performance groups and tasks are assigned according to their priority to either a high or low performance group.

摘要翻译： 一种用于使用具有不同性能特征的核的多核集成电路的方法，装置和计算机程序产品。 核心被排列成高性能组和低性能组，任务根据其优先级分配给高性能组或低性能组。

公开(公告)号：US07268570B1

公开(公告)日：2007-09-11

申请号：US11426646

申请日：2006-06-27

申请人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

发明人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

IPC分类号： G01R31/02

CPC分类号： G01R31/2855

摘要： An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

摘要翻译： 一种用于提供多核集成电路芯片的装置和方法，其降低了封装和板的成本，同时优化用于单个电压平面的芯的性能。 说明性实施例的装置和方法使用动态老化技术，其优化芯片上的所有核心以在单个电压下以峰值性能运行。 每个核心都具有定制的老化电压，可在整个芯片上提供均匀的功率和性能。 这导致集成电路芯片中更高的老化成本和更低的总功率。 通过使用负偏置温度不稳定性影响由所施加的老化电压施加的磁芯，可以实现在单电压下以峰值性能运行的磁芯的优化。

公开(公告)号：US20080178127A1

公开(公告)日：2008-07-24

申请号：US11624868

申请日：2007-01-19

申请人： Thomas J Dewkett ,  Joanne Ferris ,  Raymond J. Rosner ,  Michael J. Shapiro

发明人： Thomas J Dewkett ,  Joanne Ferris ,  Raymond J. Rosner ,  Michael J. Shapiro

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/68

摘要： A tool is provided that determines an optimal number of processor cores or other redundant units in a multiple core processor or system on a chip, along with selecting an associated semiconductor technology and integrated circuit package. The tool integrates design elements, performance and power metrics, manufacturing yields, redundancy, and costs that are both dependent and independent of design features, integrated circuit volume distributions, and boundary conditions, all for a variety of semiconductor technologies and packages. The tool may determine an optimal number of cores for a multiple core processor based on minimizing cost per unit performance or power or redundancy, or other designated design metric, and an associated volume distribution in each technology selected for manufacturing.

摘要翻译： 提供了一种工具，其确定芯片上的多核心处理器或系统中的处理器核心或其他冗余单元的最佳数量，以及选择相关联的半导体技术和集成电路封装。 该工具集成了设计元素，性能和功耗指标，制造产量，冗余和成本，这两者都依赖于设计特征，集成电路体积分布和边界条件，适用于各种半导体技术和封装。 该工具可以基于最小化每单位性能或功率或冗余度的成本或其他指定的设计度量以及选择用于制造的每种技术中的相关联的体积分布来确定多核心处理器的最佳核心数量。

公开(公告)号：US20080052542A1

公开(公告)日：2008-02-28

申请号：US11466891

申请日：2006-08-24

申请人： Louis Bennie Capps ,  Warren D. Dyckman ,  Joanne Ferris ,  Anand Haridass ,  James Douglas Jordan ,  Ronald Edward Newhart ,  Michael Richard Ouellette ,  Michael Jay Shapiro

发明人： Louis Bennie Capps ,  Warren D. Dyckman ,  Joanne Ferris ,  Anand Haridass ,  James Douglas Jordan ,  Ronald Edward Newhart ,  Michael Richard Ouellette ,  Michael Jay Shapiro

IPC分类号： G06F1/00

CPC分类号： G06F1/26

摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

公开(公告)号：US07721119B2

公开(公告)日：2010-05-18

申请号：US11466891

申请日：2006-08-24

申请人： Louis Bennie Capps, Jr. ,  Warren D. Dyckman ,  Joanne Ferris ,  Anand Haridass ,  James Douglas Jordan ,  Ronald Edward Newhart ,  Michael Richard Ouellette ,  Michael Jay Shapiro

发明人： Louis Bennie Capps, Jr. ,  Warren D. Dyckman ,  Joanne Ferris ,  Anand Haridass ,  James Douglas Jordan ,  Ronald Edward Newhart ,  Michael Richard Ouellette ,  Michael Jay Shapiro

IPC分类号： G06F1/00

CPC分类号： G06F1/26

摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

公开(公告)号：US20060235807A1

公开(公告)日：2006-10-19

申请号：US10907874

申请日：2005-04-19

申请人： Joanne Ferris

发明人： Joanne Ferris

IPC分类号： G06F17/00

CPC分类号： G06Q30/02 ,  G06Q30/0283

摘要： A method of calculating a competitive base wafer cost for use in a model for calculating a packaged integrated circuit (IC) cost. The method includes determining a base wafer price for a first wafer technology at a desired time of analysis and applying a competitive wafer gross margin for the desired time of analysis to the base wafer price to determine the competitive base wafer cost.

摘要翻译： 一种用于计算封装集成电路（IC）成本的模型中使用的竞争性基础晶圆成本的方法。 该方法包括在期望的分析时间确定第一晶圆技术的基底晶片价格，并将所需分析时间的竞争晶片毛利率应用于基础晶圆价格以确定竞争性基底晶圆成本。