Systems and methods for trimming control transistors for 3D NAND flash
    2.
    发明授权
    Systems and methods for trimming control transistors for 3D NAND flash 有权
    用于微调3D NAND闪存的控制晶体管的系统和方法

    公开(公告)号:US09324437B2

    公开(公告)日:2016-04-26

    申请号:US14446866

    申请日:2014-07-30

    Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.

    Abstract translation: 3D NAND闪存阵列内的控制晶体管和存储单元都可以使用相同的技术(如电荷俘获结构)来创建,以简化制造过程。 然而,与传统的基于栅极氧化物的控制晶体管相比,所得到的控制晶体管最初可能具有较高的阈值电压可变性。 提供了在阵列操作期间修整控制晶体管以提供增加的可靠性和性能的示例性技术。

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