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公开(公告)号：US20240363176A1
公开(公告)日：2024-10-31
申请号：US18638788
申请日：2024-04-18
申请人： Kioxia Corporation
CPC分类号： G11C16/3404 , G11C11/223 , G11C11/2275 , G11C16/0483 , G11C16/10 , G11C16/16 , H10B43/27 , H10B51/20
摘要： A semiconductor memory device of embodiments includes a semiconductor layer, a gate electrode layer, memory cells each including a gate insulating layer containing Si, O, and N, and a control circuit. The control circuit performs a write operation and an erase operation on the memory cells. The control circuit determine whether or not the number of times of execution of the erase operation on the memory cells has reached a predetermined number of times. When the number has reached the predetermined number of times, the control circuit perform first processing and second processing on the memory cells. The first processing applies a voltage with the same polarity as that in the write operation to the gate electrode layer with a pulse width larger than that in the write operation. The second processing applies a voltage with a polarity opposite to that in the write operation to the gate electrode layer.
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公开(公告)号：US20240363166A1
公开(公告)日：2024-10-31
申请号：US18766000
申请日：2024-07-08
申请人： Kioxia Corporation
发明人： Hiroshi SUKEGAWA , Ikuo MAGAKI , Tokumasa HARA , Shirou FUJITA
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/3418 , H10B43/27
摘要： A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
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公开(公告)号：US12125528B2
公开(公告)日：2024-10-22
申请号：US17896929
申请日：2022-08-26
申请人： KIOXIA CORPORATION
发明人： Naofumi Abiko
CPC分类号： G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.
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公开(公告)号：US12119062B2
公开(公告)日：2024-10-15
申请号：US17884113
申请日：2022-08-09
CPC分类号： G11C16/08 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/10 , G11C16/3459 , G11C16/0483
摘要： Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.
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公开(公告)号：US12112071B2
公开(公告)日：2024-10-08
申请号：US18217063
申请日：2023-06-30
发明人： Seonkyoo Lee , Jeongdon Ihm , Chiweon Yoon , Byunghoon Jeong
CPC分类号： G06F3/0659 , G06F1/06 , G06F3/0613 , G06F3/0679 , G06F13/1668 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20240331785A1
公开(公告)日：2024-10-03
申请号：US18739530
申请日：2024-06-11
发明人： Kyung-Min KANG , Dongku KANG , Su Chang JEON , Won-Taeck JUNG
CPC分类号： G11C16/3481 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/30
摘要： A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.
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7.发明公开公开(公告)号：US20240321366A1
公开(公告)日：2024-09-26
申请号：US18734833
申请日：2024-06-05
发明人： Kun-Woo Song , Jonghwa Kim , Kyungyong Jeoung
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/34 , G11C16/10 , G11C16/26 , H10B43/27
摘要： Disclosed is a storage device, which includes a nonvolatile memory device including a first memory block connected with a plurality of first word lines, and a memory controller connected with the nonvolatile memory device through a plurality of data lines. The memory controller sends a first command to the nonvolatile memory device through the plurality of data lines during a first command input period, sends a parameter to the nonvolatile memory device through the plurality of data lines during an address input period, and sends a second command to the nonvolatile memory device through the plurality of data lines during a second command input period. The nonvolatile memory device applies a turn-on voltage to all the plurality of first word lines connected with the first memory block based on the parameter during a first time in response to the first command and the second command.
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公开(公告)号：US20240321348A1
公开(公告)日：2024-09-26
申请号：US18675257
申请日：2024-05-28
申请人： KIOXIA CORPORATION
发明人： Naomi TAKEDA , Masanobu SHIRAKAWA , Akio SUGAHARA
CPC分类号： G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G06F12/0246
摘要： According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
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公开(公告)号：US12100459B2
公开(公告)日：2024-09-24
申请号：US18333661
申请日：2023-06-13
申请人： KIOXIA CORPORATION
发明人： Shinya Okuno , Shigeki Nagasaka , Toshiyuki Kouchi
IPC分类号： G11C16/04 , G06F5/06 , G06F13/16 , G11C7/02 , G11C7/10 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/32
CPC分类号： G11C16/32 , G06F5/06 , G06F13/1673 , G11C7/02 , G11C7/1012 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G06F2205/067 , G11C16/0483 , G11C2207/108 , G11C2207/2281 , Y02D10/00
摘要： A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
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公开(公告)号：US20240315028A1
公开(公告)日：2024-09-19
申请号：US18604200
申请日：2024-03-13
发明人： Paolo Tessariol , Aaron S. Yip , Giovanni Mazzone , Matthew King
CPC分类号： H10B43/27 , G11C16/0483 , G11C16/10 , H10B41/27
摘要： A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.
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